Systematic Methodology To Solve Reset Challenges In Automotive SoCs


Modern automotive SoCs typically contain multiple asynchronous reset signals to ensure systematic functional recovery from unexpected situations and faults. This complex reset architecture leads to a new set of problems such as possible reset domain crossing (RDC) issues. The conventional clock domain and CDC verification methodologies cannot identify such critical bugs. In this paper, we prese... » read more

Shift Left Power-Aware Static Verification


Next-generation SoCs with advanced graphics, computing, machine learning (ML) and artificial intelligence (AI) capabilities are posing new unseen challenges in Low Power Verification. These techniques can introduce critical bugs into a design, especially when the power-management infrastructure interacts with signals that cross clock or reset domains. This can create additional clock-domain cro... » read more

Resets And Reset Domain Crossings In ASIC And FPGA Designs


This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification. To download this paper, clic... » read more

Respecting Reset


Resets are a necessary part of all synchronous designs because they allow them to be brought into a known state. However, such a simple process can lead to many problems within an [getkc id="81" kc_name="SoC"]. No longer can reset be considered a simple operation when power initially is applied to a circuit. Instead, the design of reset has many implications on cost, area and routability, a... » read more

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