High-Level Synthesis For RISC-V

By Brian Bailey - 28 Oct, 2021 - Comments: 2

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL). There are two types of high-level synthesis (HLS) that need to be considered. The first is ge... » read more

Customize Off-The-Shelf Processor IP

By Roddy Urquhart - 28 Oct, 2021 - Comments: 0

Processor customization is one approach to optimizing a processor IP core to handle a certain workload. In some case it makes sense to design a dedicated core from scratch, but in many cases an existing core may partially meet your requirements and can be a good starting point for your optimized core. In the past some processor IP vendors, notably ARC and Tensilica, offered extensible cores ... » read more

Optimization Driving Changes In Microarchitectures

By Ann Mutschler - 23 Sep, 2021 - Comments: 0

The semiconductor ecosystem is at a turning point for how to best architect the CPU based on the explosion of data, the increased usage of AI, and the need for differentiation and customization in leading-edge applications. In the past, much of this would have been accomplished by moving to the next process node. But with the benefits from scaling diminishing at each new node, the focus is s... » read more

Why It’s The Perfect Time To Be Part Of The RISC-V Revolution

By Rupert Baines - 23 Sep, 2021 - Comments: 1

Eighteen months ago, I said: “The rise of RISC-V offers us a tremendous platform for innovation and collaboration: it has the potential to change the business model of the entire industry.” I stand by that and indeed am demonstrating my conviction by joining the ranks of a company that’s not only changing the industry business model, but is significantly innovating in RISC-V. Having ... » read more

RISC-V Processor Verification: Case Study

By Imperas - 22 Sep, 2021 - Comments: 0

Abstract: The open RISC-V instruction set architecture is gaining traction with both semiconductor vendors and systems companies. A key question is how to verify the RISC-V processor implementation, especially when developing the RTL and/or adding custom instructions? This paper reports on the techniques used and lessons learned for the verification of a RV64IMACBNSU RISC-V processor by an exp... » read more

On the Design and Misuse of Microcoded (Embedded) Processors — A Cautionary Note

By Technical Paper Link - 08 Sep, 2021 - Comments: 0

Abstract: "Today's microprocessors often rely on microcode updates to address issues such as security or functional patches. Unfortunately, microcode update flexibility opens up new attack vectors through malicious microcode alterations. Such attacks share many features with hardware Trojans and have similar devastating consequences for system security. However, due to microcode's opaq... » read more

58th DAC Online Program Is Now Live

By Michelle Clancy - 31 Aug, 2021 - Comments: 0

We did it. After more than a year’s worth of hard work the DAC Executive Committee finally released the 58th DAC program, despite a mountain of challenges and hurdles we encountered along the way this past year. We started planning the 58th DAC a little over a year ago, and we were confronted with a lot of uncertainty on what to expect for the coming year. Would submissions be down? Would ... » read more

New Approaches For Processor Architectures

By Ed Sperling - 26 Aug, 2021 - Comments: 0

Processor vendors are starting to emphasize microarchitectural improvements and data movement over process node scaling, setting the stage for much bigger performance gains in devices that narrowly target what end users are trying to accomplish. The changes are a recognition that domain specificity, and the ability to adjust or adapt designs to unique workloads, are now the best way to impro... » read more

The Difference Between Processor Configuration And Customization

By Roddy Urquhart - 26 Aug, 2021 - Comments: 0

For many years, people have been talking about configuring processor IP cores, but especially with growing interest in the open RISC-V ISA, there is much more talk about customization. So, what is the difference? A simple analogy is to think of ordering a pizza. With most pizzerias, you have standard bases and a choice of toppings from a limited list. You can configure the pizza to the ... » read more

Working With RISC-V

By Ed Sperling - 17 Aug, 2021 - Comments: 0

RISC-V is coming on strong, but working with this open-source processor core isn't as simple as plugging in a commercial piece of IP. Zdenek Prikryl, CTO at Codasip, talks about utilizing hypervisors and open source tools and extensions to the RISC-V instruction set architecture, where design teams can run into problems, what will change as the architecture becomes more mature, the difference b... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: RISC-V