The Challenge Of RISC-V Compliance

By Brian Bailey - 28 Feb, 2019 - Comments: 0

The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that ... » read more

The Rapid Rise Of RISC-V

By Andy Gothard - 28 Feb, 2019 - Comments: 0

The first RISC-V Summit, which took place last month in Santa Clara, CA, appears to be a watershed for the RISC-V ecosystem. The technology is maturing and the ecosystem is growing fast – and that was reflected in the nature of the presentations and news announcements we saw. The accent has started to move to how the technology will be used in real life. UltraSoC’s announcement of a har... » read more

How to Connect Questa VIP to the Processor Verification Flow

By Codasip - 27 Feb, 2019 - Comments: 0

Learn how to incorporate Questa VIP into your existing RISC-V verification flow. This step-by-step tutorial, prepared by Codasip’s verification experts, explains the concepts of combining automatically generated UVM with QVIP and guides you through the process. Read more here. » read more

Week In Review: Design, Low Power

By Jesse Allen - 22 Feb, 2019 - Comments: 0

Tools OneSpin unveiled a set of formal apps for development and assessment of RISC-V cores. The RISC-V Integrity Verification Solution formalizes the RISC-V ISA in a set of SystemVerilog Assertions to verify compliance for the ISA is met. It provides a formal bug absence core assessment environment for unbounded proofs and systematic discovery of all hidden instructions or unintended side effe... » read more

Meltdown And Spectre, One Year Later

By Paul Kocher - 11 Feb, 2019 - Comments: 0

About this time last year, reports surfaced about security attacks on today’s most popular microprocessors (μPs). Researchers called them Meltdown, Spectre gaining widespread attention. Today, however, the industry and especially μP vendors have made some progress toward stemming these vulnerabilities. Here is my analysis as we enter into 2019. When it comes to these vulnerabilities, we ... » read more

Week in Review: Design, Low Power

By Susan Rambo - 08 Feb, 2019 - Comments: 0

The U.S. Department of Energy (DOE) has awarded $35 million for 12 projects involving ultra-efficient power management. Called Arpa-E, the program encouraged participants to use medium-voltage electricity in new ways with real-world applications, such as industry, transportation and the grid. The top two award winners were Eaton Corp. (Arden, NC) for its DC wide-bandgap static circuit breaker, ... » read more

Week In Review: Design, Low Power

By Jesse Allen - 01 Feb, 2019 - Comments: 0

Tools & IP OneSpin revealed its latest formal app, Connectivity XL, providing formal connectivity checking to 7nm, multi-billion gate SoC designs. The app generates detailed connectivity specification tables from abstract connectivity specs through a dedicated checking engine that integrates structural and formal analysis to perform on-the-fly, automated abstractions. It supports verificat... » read more

Using Memory Differently

By Ann Mutschler - 31 Jan, 2019 - Comments: 0

Chip architects are beginning to rewrite the rules on how to choose, configure and use different types of memory, particularly for chips with AI and some advanced SoCs. Chipmakers now have a number of options and tradeoffs to consider when choosing memories, based on factors such as the application and the characteristics of the memory workload, because different memory types work better tha... » read more

EDA Grabs Bigger Slice Of Chip Market

By Brian Bailey - 31 Jan, 2019 - Comments: 0

EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Building Security Into RISC-V Systems

By Ed Sperling - 30 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down with Helena Handschuh, a Rambus fellow; Richard Newell, senior principal product architect at Microsemi, a Microchip Company; and Joseph Kiniry, principal scientist at Galois. Part one is here. (This is the second of two parts.) L-R: Joseph Kiniry, Helena Handschuh, Richard Newell. SE: Some of the new applications for hardware designs are tied to AI, d... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

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tag: RISC-V

The Challenge Of RISC-V Compliance

The Rapid Rise Of RISC-V

How to Connect Questa VIP to the Processor Verification Flow

Week In Review: Design, Low Power

Meltdown And Spectre, One Year Later

Week in Review: Design, Low Power

Week In Review: Design, Low Power

Using Memory Differently

EDA Grabs Bigger Slice Of Chip Market

Building Security Into RISC-V Systems