tag: RISC-V

RISC-V At Embedded World
By Jo Windel - 28 Mar, 2019 - Comments: 0

As we arrive back from a busy, and unusually warm, Embedded World 2019 and recall the many interesting discussions we had over the three-day show, one thing is most certainly clear: This is the Mobile World Congress (MWC) event for Nuremberg. Its many halls were jam-packed with technology from a wide variety of sectors but also with an array of application focal points. There was everything ... » read more

The Other Side Of Makimoto’s Wave
By Ann Mutschler - 06 Mar, 2019 - Comments: 0

Custom hardware is undergoing a huge resurgence across a variety of new applications, pushing the semiconductor industry to the other side of Makimoto's Wave. Tsugio Makimoto, the technologist who identified the chip industry’s 10-year cyclical swings between standardization and customization, predicted there always will be room in ASICs for general-purpose processors. But it's becoming mo... » read more

Formal Verification Of RISC-V Cores
By Sven Beyer - 28 Feb, 2019 - Comments: 0

RISC-V is hot and stands at the beginning of what may be a major shift in the industry. Even a cursory review of upcoming conferences programs and recent technical articles makes that clear. While it is still early in the evolution of the processor architecture, there is certainly the potential that RISC-V will be a game-changer in the IP and semiconductor industry. As “a free and open ISA en... » read more

The Challenge Of RISC-V Compliance
By Brian Bailey - 28 Feb, 2019 - Comments: 0

The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that ... » read more

The Rapid Rise Of RISC-V
By Andy Gothard - 28 Feb, 2019 - Comments: 0

The first RISC-V Summit, which took place last month in Santa Clara, CA, appears to be a watershed for the RISC-V ecosystem. The technology is maturing and the ecosystem is growing fast – and that was reflected in the nature of the presentations and news announcements we saw. The accent has started to move to how the technology will be used in real life. UltraSoC’s announcement of a har... » read more

How to Connect Questa VIP to the Processor Verification Flow
By Codasip - 27 Feb, 2019 - Comments: 0

Learn how to incorporate Questa VIP into your existing RISC-V verification flow. This step-by-step tutorial, prepared by Codasip’s verification experts, explains the concepts of combining automatically generated UVM with QVIP and guides you through the process. Read more here. » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Feb, 2019 - Comments: 0

Tools OneSpin unveiled a set of formal apps for development and assessment of RISC-V cores. The RISC-V Integrity Verification Solution formalizes the RISC-V ISA in a set of SystemVerilog Assertions to verify compliance for the ISA is met. It provides a formal bug absence core assessment environment for unbounded proofs and systematic discovery of all hidden instructions or unintended side effe... » read more

Meltdown And Spectre, One Year Later
By Paul Kocher - 11 Feb, 2019 - Comments: 0

About this time last year, reports surfaced about security attacks on today’s most popular microprocessors (μPs). Researchers called them Meltdown, Spectre gaining widespread attention. Today, however, the industry and especially μP vendors have made some progress toward stemming these vulnerabilities. Here is my analysis as we enter into 2019. When it comes to these vulnerabilities, we ... » read more

Week in Review: Design, Low Power
By Susan Rambo - 08 Feb, 2019 - Comments: 0

The U.S. Department of Energy (DOE) has awarded $35 million for 12 projects involving ultra-efficient power management. Called Arpa-E, the program encouraged participants to use medium-voltage electricity in new ways with real-world applications, such as industry, transportation and the grid. The top two award winners were Eaton Corp. (Arden, NC) for its DC wide-bandgap static circuit breaker, ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 01 Feb, 2019 - Comments: 0

Tools & IP OneSpin revealed its latest formal app, Connectivity XL, providing formal connectivity checking to 7nm, multi-billion gate SoC designs. The app generates detailed connectivity specification tables from abstract connectivity specs through a dedicated checking engine that integrates structural and formal analysis to perform on-the-fly, automated abstractions. It supports verificat... » read more

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