tag: RTL simulation

Modeling And Analyzing Open-Source SoCs For Low-Power Cyber-Physical Systems
By Technical Paper Link - 08 Feb, 2024 - Comments: 0

A technical paper titled “TOP: Towards Open & Predictable Heterogeneous SoCs” was published by researchers at University of Bologna, ETH Zurich, and University of California San Diego. Abstract: "Ensuring predictability in modern real-time Systems-on-Chip (SoCs) is an increasingly critical concern for many application domains such as automotive, robotics, and industrial automation. An... » read more

Hardware-Accelerated RTL Simulator
By Technical Paper Link - 26 Apr, 2023 - Comments: 0

A technical paper titled "Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism" was published by researchers at EPFL, University of Tokyo, Sharif University, and Indian Institute of Technology. Abstract "The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of thi... » read more

Who Does Processor Validation?
By Brian Bailey - 27 Jun, 2022 - Comments: 1

Defining what a processor is, and what it is supposed to do, is not always as easy as it sounds. In fact, companies are struggling with the implications of hundreds of heterogenous processing elements crammed into a single chip or package. Companies have extensive verification methodologies, but not for validation. Verification is a process of ensuring that an implementation matches a specif... » read more

Finding Code Problems Before High-Level Synthesis
By Mentor, a Siemens Business - 10 Apr, 2019 - Comments: 0

In order to significantly speed up verification and to handle complex algorithms that change daily, many companies are turning to a High-Level Synthesis (HLS) methodology. But, it is extremely important that the high-level C++ model is correct. In addition, the C++ language has ambiguities that can be tough to catch during simulation. Even if correctly written, the high-level model could be cod... » read more

Getting A Handle On RTL X-Verification Challenges
By Graham Bell - 27 Mar, 2014 - Comments: 1

The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout.  Some engineers point out that we have always had to deal with X’s and nothing has really changed. In fact, today’s SoC employ different power management schemes that wake-up or suspend IP.  As any designer knows, when powering ... » read more

Know What To Look For
By Ann Mutschler - 13 Mar, 2014 - Comments: 0

With the number of power domains exploding in today’s ICs, it’s extremely difficult to include all different modes of complexity in the verification. “The problem was already challenging enough,” observed Mark Baker, director of product marketing at Atrenta. “Just looking at where SoC design was going was a collection of various IPs, the different communication protocols, the bus ... » read more

Aren’t We Beyond That?
By Ann Mutschler - 21 Jul, 2011 - Comments: 0

The latest and greatest technologies always get the most attention because they are new and fresh, but gate-level simulation—a long-time workhorse tool—is seeing a small comeback with designers as of late. According to Cadence’s Pete Hardee, even though the industry is spending a lot of time looking ahead to architectural-level power modeling and virtual prototyping, the need for detai... » read more

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