Does SoC Signoff Mean More Than RTL?


As the cost of failure continues to rise, SoC engineers see the growing importance of ensuring their work is as correct as possible as soon as possible in the design process. They cannot afford to carry errors forward from one stage to the next, where their impact grows while their causes become more obscured. This requirement is driving the shift in design exploration and handoff to the reg... » read more

Optimizing IP For Power


By Ed Sperling As the amount of commercial IP in an SoC increases, the entire bill of materials is coming under increasing scrutiny because of a new concern—power. Commercial IP, after all, is largely a collection of black-box solutions to speed up the time it takes to bring a chip to market, and frequently to improve the quality, but the cumulative impact on the system power budget has neve... » read more

RTL Restructuring


We all know that hierarchy created for logic design must often be adjusted to map to a physical implementation. Logic hierarchy is typically constrained by non-implementation factors, especially organization of teams working on different components and use of legacy or 3rd party IP. Physical hierarchy, on the other hand, must partition the logic to fit detailed implementation tool capacity limi... » read more

Experts At The Table: The Trouble With Low-Power Verification


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

Experts At The Table: The Trouble With Low-Power Verification


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

RTL Design-For-Power Methodology


This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power. To download this white paper, click here. » read more

RTL Design-for-Power Methodology


This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power. To view this white paper, click here. » read more

Show Me


By Jon McDonald Many people—engineers especially, myself included—are naturally biased against change. To get an organization to change takes significant energy. This isn’t a new trend. Much of the sentiment of the camp against change can be summed up by referring back to an 1899 quote from Missouri Sen. Willard Vandiver: “… frothy eloquence neither convinces nor satisfies me. I am f... » read more

An Automated Approach To RTL Memory BIST Insertion And Verification


ASIC vendors have been traditionally incorporating built-in self test (BIST) and repair solutions in their customers' gate level netlist. This used to be the common industry practice for technology nodes of 65 nm and older. Designers were comfortable writing in-house Perl scripts to replace memory instances with combined memory-BIST (MBIST) instances and make necessary connections. However, for... » read more

RTL Power Reduction Triathlon


Unless you’ve just come out of a week-long coma, you’ve been watching at least part of the Olympic Games in London. The years of training, the drama of competition, the thrill of victory… (you know the rest). Some contests come down to the smallest of margins to define who wins gold. The recent women’s triathlon is one such case. After a 500-meter swim, a 43-kilometer bike ride and a 10... » read more

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