tag: Samsung

Hybrid Bonding Moves Into The Fast Lane
By Laura Peters - 21 Jul, 2022 - Comments: 1

The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

Film Failure in Multilayer Systems for Semiconductor Devices
By Technical Paper Link - 18 Jul, 2022 - Comments: 0

Researchers at MIT, Yonsei University (Seoul, Korea) just published this technical paper titled "Interfacial Delamination at Multilayer Thin Films in Semiconductor Devices." According to the abstract "In this work, the effect of thermomechanical stress on the failure of multilayered thin films on Si substrates was studied using analytical calculations and various thermomechanical tests." ... » read more

Week In Review, Manufacturing, Test
By Susan Rambo - 08 Jul, 2022 - Comments: 0

The U.S. is attempting to restrict sales of ASML’s deep ultra-violet (DUV) litho systems to China, according to a report from Bloomberg. The U.S. has been working to limit China's access to advanced technology for some time, and it has already limited sales of extreme ultra-violet (EUV), which is used to develop chips at the most advanced process nodes. DUV, in contrast, is used for older-nod... » read more

Week In Review: Design, Low Power
By Jesse Allen - 08 Jul, 2022 - Comments: 0

Tools, IP, design Infineon Technologies acquired NoBug, a provider of design verification services. The acquisition will help Infineon expand its IoT R&D business in eastern Europe. “This considerable increase in superior verification know-how lets Infineon offer its customers more of its leading products at a reduced time-to-market,” said Guenter Krasser, Vice President and Managing D... » read more

Week In Review, Manufacturing, Test
By Karen Heyman - 01 Jul, 2022 - Comments: 0

Samsung announced initial production of its 3nm process node, which uses a gate-all-around (nanosheet) transistor structure that the company calls Multi-Bridge-Channel FET (MBCFET). The first-generation 3nm process can reduce power consumption by up to 45% compared with a 5nm process, as well as improve performance by 23% and reduce area by 16%, according to the company. The second-generation 3... » read more

EDA Gaps At The Leading Edge
By Ed Sperling - 29 Jun, 2022 - Comments: 1

Semiconductor Engineering sat down to discuss why new approaches are required for heterogeneous designs, with Bari Biswas, senior vice president for the Silicon Realization Group at Synopsys; John Lee, general manager and vice president of the Ansys Semiconductor business unit; Michael Jackson, corporate vice president for R&D at Cadence; Prashant Varshney, head of product for Microsoft Azu... » read more

Week In Review: Manufacturing, Test
By Linda Christensen - 27 May, 2022 - Comments: 0

Broadcom announced it will acquire cloud computing and virtualization company VMware for about $61 billion in cash and stock, and assume $8 billion in VMware net debt. If all goes as planned, the Broadcom Software Group will rebrand and operate as VMware. “The combined solutions will enable customers, including leaders in all industry verticals, greater choice and flexibility to build, run, m... » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 May, 2022 - Comments: 0

EnSilica listed on the London Stock Exchange's AIM market under the ticker ENSI. EnSilica designs mixed signal ASICs for system developers in the automotive, industrial, healthcare, and communications markets. It also has a portfolio of core IP covering cryptography, radar and communications systems. AIM is the LSE’s market for small and medium sized growth companies. "In connection with Admi... » read more

Standardizing Chiplet Interconnects
By John Koon - 23 May, 2022 - Comments: 0

The chip industry is making progress on standardizing the infrastructure for chiplets, setting the stage for faster and more predictable integration of different functions and features from different vendors. The ability to choose from a menu of small, highly specialized chips, and to mix and match them for specific applications and use cases, has been on the horizon for more than a decade. ... » read more

Paving The Way To Chiplets
By Mark LaPedus - 25 Apr, 2022 - Comments: 2

The packaging industry is putting pieces in place to broaden the adoption of chiplets beyond just a few chip vendors, setting the stage for next-generation 3D chip designs and packages. New chiplet standards, and a cost analysis tool for determining the feasibility of a given chiplet-based design, are two new and important pieces. Along with other efforts, the goal is to propel the chiplet m... » read more

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