Blog Review: Apr. 25

By Jesse Allen - 25 Apr, 2018 - Comments: 0

Mentor's Cristian Filip digs into SerDes design with a focus on the adoption and evolution of Channel Operating Margin (COM) as a tool for ensuring compliance of high-speed designs and why it's useful even if its mathematical procedure might be intimidating at the beginning. Cadence's Paul McLellan explains the importance of IBIS and AMI standards for SerDes design and why the upcoming DDR5 ... » read more

The Week In Review: Design

By Jesse Allen - 20 Apr, 2018 - Comments: 0

M&A The ESD Alliance is merging with SEMI, becoming a SEMI Strategic Association Partner. SE Editor In Chief Ed Sperling argues that the merger has broad implications for the chip industry, particularly as smaller nodes require greater collaboration between design and manufacturing. Meanwhile, SEMI president and CEO Ajit Manocha explains why the combining will be of benefit to members of b... » read more

The CryptoManager Root Of Trust

By Rambus - 16 Apr, 2018 - Comments: 0

In January 2018, Meltdown and Spectre were independently disclosed by multiple security researchers, including senior Rambus technology advisor Paul Kocher and senior Rambus security engineer Mike Hamburg. The two security flaws exploit critical vulnerabilities across a wide range of modern processors, including Intel, ARM and AMD. Notably, however, existing RISC-V processors remain unaffected ... » read more

Built-In Security For Auto Chips

By Jeff Dorsch - 11 Apr, 2018 - Comments: 0

The road to autonomous vehicles depends upon components that are secured against hacking and other outside interference. The cybersecurity precautions necessary for self-driving cars must be embedded in chips and systems from the beginning of the supply chain. Automotive manufacturers and their Tier 1 suppliers are counting on their electronics vendors to provide products that can withst... » read more

Artificial, With Questionable Intelligence

By Ed Sperling - 05 Apr, 2018 - Comments: 1

A common theme is emerging in the race to develop big machines that can navigate through a world filled with people, animals, and other assorted objects—if an accident is inevitable, what options are available to machines and how should they decide? This question was raised at a number of semiconductor industry conferences over the past few weeks, which is interesting because this idea h... » read more

Securing IoT Edge Devices

By Asaf Ashkenazi - 05 Apr, 2018 - Comments: 0

It certainly isn’t any secret that the industry continues to be challenged when it comes to adopting and implementing practical IoT security solutions. However, it is important to understand that IoT edge devices typically only have basic resources, such as reduced CPU processing power and a minimal amount of RAM and flash memory. This means there are limited compute capabilities available fo... » read more

eFPGAs Accelerate Data-Centric Processing

By Alok Sanghavi - 05 Apr, 2018 - Comments: 0

With the ever-increasing requirements to manage and process enterprise data, system architects are looking closer than ever at programmable logic, a technology to make computing much more efficient and secure. While traditional processors force data into their pipelines through a complex hierarchy of caches, programmable logic makes it possible to construct data pipelines. Data can flow seam... » read more

Where Is Energy Harvesting?

By Kevin Fogarty - 05 Apr, 2018 - Comments: 0

With power management a top priority in sensor networks, why is energy harvesting—a proven technology with diverse energy sources—conspicuously absent from sensor designs that are the foundation of the Internet of Things? [getkc id="165" kc_name="Energy harvesting"] always has been a promising answer to the limits of battery power. The idea that a device can run for much longer periods o... » read more

New Market Drivers

By Brian Bailey - 05 Apr, 2018 - Comments: 2

Semiconductor Engineering sat down to discuss changing market dynamics with Steve Mensor, vice president of marketing for [getentity id="22926" e_name="Achronix"]; Apurva Kalia, vice president of R&D in the System and Verification group of [getentity id="22032" e_name="Cadence"]; Mohamed Kassem, CTO for [getentity id="22910" comment="efabless"]; Matthew Ballance, product engineer and techno... » read more

Tokenization Beyond Payments

By Rambus - 04 Apr, 2018 - Comments: 0

Tokenization is a process by which sensitive data is replaced with unique identification credentials that retain all essential information about the data without exposing said sensitive data to attacks. While traditional payment methods pass critical identification information through several points, tokenization minimizes the amount of data a business needs to keep on hand. Becoming popular wi... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?