Precision Selective Etch And The Path To 3D


Scaling (the shrinking of the tiny devices in chips such as transistors and memory cells) has never been easy, but making the next generation of advanced logic and memory devices a reality requires creating new structures at the atomic scale. When working with dimensions this small, there is little room for variation. Compounding the problem is a need to remove material isotropically, or, un... » read more

Precision Selective Etch Tools Pave The Way For The Next Technology Inflection


Over the past decade, the need for increasingly smaller, denser, more powerful chips has been driving semiconductor manufacturers to move away from planar structures in favor of increasingly complex three-dimensional (3D) structures. Why? Simply put, stacking elements vertically enables greater density. Use of 3D architectures to support advanced logic and memory applications represents the ... » read more

What’s Next For Transistors And Chiplets


Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Selective Removal For Stronger Fins


By Matt Cogorno and Toshihiko Miyashita Remember when we could charge our mobile phones on a Sunday and not even think about it again until the next weekend? There was a time when battery life wasn’t even in the top ten concerns when purchasing a mobile phone. Today however, smartphones are constantly being used for computing, gaming, video streaming and other power-hungry applications, so... » read more