What To Do About Electrostatic Discharge


Electrostatic discharge is a well-understood phenomenon, but it’s becoming more difficult to plan for as single chips are replaced by multiple chips or chiplets in a package, and as the density of components continues to increase with each new node. In both cases, the probability for failure increases unless these sudden shocks are addressed in the design. Dermott Lynch, director of product m... » read more

How Quickly Will Multi-Die Systems Change Semiconductor Design?


For many decades, semiconductor design and implementation has been focused on monolithic, ever-larger and more complex single-chip implementation. This system-on-chip approach is now changing for a variety of reasons. The new frontier utilizes many chips assembled in new ways to deliver the required form-factor and performance. Multi-die systems are paving the way for new types of semiconduc... » read more

Everyone’s A System Designer With Heterogeneous Integration


The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing. Nearly every engineer is now working or touching some technology, process, or methodology that is new. And they are inter... » read more

Ansys Charge Plus And Its Particle-In-Cell Solver


SIMULATING SEMICONDUCTORS PARTICLE BY PARTICLE Plasma enhanced chemical vapor deposition (PE-CVD) and plasma etching are experimental techniques that leverage multiphysics for product development in the semiconductor industry. PE-CVD explicitly tackles the deposition of material on the surface of a wafer, such as a thin coating. A chemical with free radicals is placed on the surface of the ... » read more

Shift Left, Extend Right, Stretch Sideways


The EDA industry has been talking about shift left for a few years, but development flows are now being stretched in two additional ways, extending right to include silicon lifecycle management, and sideways to include safety and security. In addition, safety and security join verification and power as being vertical concerns, and we are increasingly seeing interlinking within those concerns. ... » read more

CEO Outlook: Chiplets, Data Management, And Reliability


Semiconductor Engineering sat down to talk about changes in chip design with Joseph Sawicki, executive vice president for IC EDA at Siemens Digital Industries Software; John Kibarian, president and CEO of PDF Solutions; John Lee, general manager and vice president of Ansys' Semiconductor Business Unit; Niels Faché, vice president and general manager of PathWave Software Solutions at Keysight; ... » read more

Managing EDA’s Rapid Growth Expectations


The EDA industry has been doing very well recently, but how long this run will continue is a matter of debate. EDA is an industry ripe for disruption due to rapid changes in chip architectures, end markets, and a long list of new technologies. In addition, recent geopolitical tensions are bringing a lot more attention to this small sector upon which the whole semiconductor industry rests. De... » read more

Improving PPA When Embedding FPGAs Into SoCs


Embedded FPGAs have been on everyone’s radar for years as a way of extending the life of chips developed at advanced nodes, but they typically have come with high performance and power overhead. That’s no longer the case, and the ability to control complex chips and keep them current with changes to algorithms and various protocols is significant step. Geoff Tate, CEO of Flex Logix, talks a... » read more

Reducing Simulation Regression Turnaround Time With Dynamic Performance Optimization


No single step in the development of semiconductor devices is more sensitive to speed than functional simulation. A modern system-on-chip (SoC) design simulates billions of cycles of operation in the process of completing the verification plan and achieving coverage goals. To validate full system functionality, many of these simulations include running code on one or more embedded processors. E... » read more

Improving Concurrent Chip Design, Manufacturing, And Test Flows


Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale. The glue between these various processes is data, and the chip industry is working to weave together various steps t... » read more

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