The Week In Review: Design

By Ed Sperling - 04 Apr, 2014 - Comments: 0

Tools Mentor Graphics rolled out a new platform for verification of unknown voltage levels (Xs) at the register transfer and gate levels, fusing together simulation and formal verification under one umbrella. The company says the approach will limit bugs and wasted effort caused by X-optimism and pessimism. Jasper Design Automation unveiled a new tool to verify the sequential functional equ... » read more

Tech Talk: Multipatterning, Take Two

By Brian Bailey - 31 Mar, 2014 - Comments: 0

Mentor Graphics' David Abercrombie continues with his whiteboard talk about coloring with advanced lithography, including what goes wrong and how to fix it. [youtube vid=HCBtvHCcbf4] » read more

Tech Talk: Security Risks In An SoC

By Ed Sperling - 02 Dec, 2013 - Comments: 1

Lawrence Loh, vice president of engineering at Jasper Design Automation, maps out the security threats in complex systems on chip. [youtube vid=5GBYOnCBfEE] » read more

Executive Briefing: Prakash Narain

By Ed Sperling - 12 Jul, 2013 - Comments: 0

Real Intent CEO Prakash Narain talks with System-Level Design about where are the pain points in verification; different types of signoff; the impact of third-party IP, and can the tools industry keep up with the rising complexity in semiconductor design. [youtube vid=C25VMRDXGAQ] » read more

Foundry Talk

By Ed Sperling - 07 Jul, 2013 - Comments: 0

GlobalFoundries CEO Ajit Manocha sounds off on Foundry 2.0, 450mm wafers, lithography challenges, stacked die, the Internet of Things and the rush to the next process node. [youtube vid=WfjtlZkCi0w] » read more

Executive Briefing: Stacking The Odds

By Ed Sperling - 29 May, 2013 - Comments: 0

Open-Silicon CEO Naveed Sherwani talks with System-Level Design about progress on 2.5D and 3D stacked die, why this approach is inevitable, when it will begin and what markets will use it first. [youtube vid=mzwpgDKuIok] » read more

Bigger Wafers, Bigger Risk

By Ed Sperling - 16 May, 2013 - Comments: 0

At 22/20/16/14nm the semiconductor industry is experiencing a rather new twist on Moore’s Law. Smaller, as in smaller feature sizes, is no longer assumed to be cheaper—or at least not for everyone. In fact, the cost per transistor for the first time in more than half a century could rise in some cases. Whether this outlook improves as the semiconductor industry gains more experience wit... » read more

FinFETs On SOI

By Ed Sperling - 13 May, 2013 - Comments: 0

Soitec's Steve Longoria talks with Semiconductor Manufacturing and Design about what's changing at the leading edge of Moore's Law and why those changes are necessary. [youtube vid=K6D39QqJWSU] » read more

Divide, Abstract And Conquer

By Ed Sperling - 03 May, 2013 - Comments: 0

For years, the motto among design and verification engineers has been to look at the individual pieces of a design because it’s impossible to have a single tool or even an integrated collection of tools that can debug everything. That approach isn’t changing, but the method for getting there is. The driver behind this shift is a familiar one—growing complexity. Even platforms and subsy... » read more

MEMS Explosion

By Rakesh Kumar - 18 Apr, 2013 - Comments: 0

By Rakesh Kumar The MEMS market is set to explode. By 2017 the market is expected to be worth $12.2 billion, a 50% increase from 2011, according to IHS iSuppli. Driving this growth will be the continued usage of MEMs devices for consumer applications, such as smartphones, tablets, gaming consoles and cameras. Additionally, new products such as silicon timing devices, tunable capacitors for ant... » read more

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