tag: Seoul National University

Scalable Approach For Fabricating Sub-10nm Nanogaps
By Technical Paper Link - 07 Apr, 2025 - Comments: 0

A new technical paper titled "A progressive wafer scale approach for Sub-10 nm nanogap structures" was published by researchers at Seoul National University, Chung-Ang University, Mohammed VI Polytechnic University and Ulsan National Institute of Science and Technology. "We have advanced the atomic layer lithography method into an efficient, scalable approach for fabricating sub-10 nm nanoga... » read more

Chip Industry Technical Paper Roundup: Mar. 25
By Linda Christensen - 25 Mar, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=415 /] Find more semiconductor research papers here. » read more

EFO Errors In The Wire-Bonding Semiconductor Packaging Process
By Technical Paper Link - 19 Mar, 2025 - Comments: 0

A new technical paper titled "A Comparative Study on Various Au Wire Rinse Compositions and Their Effects on the Electronic Flame-Off Errors of Wire-Bonding Semiconductor Package" was published by researchers at Hanbat National University, Seoul National University and Chungnam National University. The paper states: "In this study, we identify the origin of electronic flame-off (EFO) erro... » read more

A Novel Tier Partitioning Method in 3DIC Placement Optimizing PPA
By Technical Paper Link - 11 Mar, 2025 - Comments: 0

A new technical paper titled "PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation" was published by researchers at Seoul National University and Ulsan National Institute of Science and Technology. Abstract "3D ICs are renowned for their potential to enable high-performance and low-power designs by utilizing denser and shorter inter-tier connections. In the physical design f... » read more

Research Bits: Mar. 10
By Jesse Allen - 10 Mar, 2025 - Comments: 0

Incipient ferroelectricity Researchers from Penn State University and the University of Minnesota propose harnessing incipient ferroelectricity in multifunctional two-dimensional FETs to create neuromorphic computer memory. Materials with incipient ferroelectricity have no stable ferroelectric order at room temperature and need certain conditions to achieve an electrical charge. The FETs were ... » read more

Research Bits: Jan. 20
By Jesse Allen - 20 Jan, 2025 - Comments: 0

Self-correcting memristor array Researchers at Korea Advanced Institute of Science and Technology (KAIST), Seoul National University, Sungkyunkwan University, Electronics and Telecommunications Research Institute (ETRI), and Yonsei University developed a memristor-based neuromorphic chip that can learn and correct errors, enabling it to adapt to immediate environmental changes. The system c... » read more

Research Bits: Jan. 13
By Jesse Allen - 13 Jan, 2025 - Comments: 0

High-temp electrochemical memory Researchers from the University of Michigan and Sandia National Laboratory propose a nonvolatile electrochemical memory that can store and rewrite information at temperatures over 1100°F (600°C), enabling it to continue working in environments as extreme as the surface of Venus. Instead of transporting electrons, the memory moves oxygen ions between layere... » read more

Chip Industry Week In Review
By The SE Staff - 20 Dec, 2024 - Comments: 0

Updated for 12/20 government fundings and 12/23 for China trade investigation announcements. President Biden announced a trade investigation into "China's unfair trade practices in the semiconductor sector."  The announcement stated "PRC semiconductors often enter the U.S. market as a component of finished goods. This Section 301 investigation will examine a broad range of the PRC’s non-m... » read more

Chip Industry Technical Paper Roundup: Nov. 11
By Linda Christensen - 11 Nov, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=381 /] More Reading Technical Paper Library » read more

Review of Advances in 3D integration of 2D Neuromorphic Electronics, Materials to Systems
By Technical Paper Link - 05 Nov, 2024 - Comments: 0

A new technical paper titled "2D materials-based 3D integration for neuromorphic hardware" was published by researchers at  Seoul National University and University of Southern California. Find the technical paper here. November 2024. Kim, S.J., Lee, HJ., Lee, CH. et al. 2D materials-based 3D integration for neuromorphic hardware. npj 2D Mater Appl 8, 70 (2024). https://doi.org/10.10... » read more

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