tag: SerDes

What Is Electronic Design Automation And Why Do You Need It?
By Roberto Piacentini Filho - 24 Apr, 2025 - Comments: 0

As data speeds push into the multi-gigabit range and requirements on digital systems grow more complex, cutting down the time-to-market while also ensuring error-free reliable designs seems impossible. Traditional design tools and practices can result in failed prototypes, costly respins, delayed time-to-market, missed market opportunities, and subpar performance. This is why advanced EDA to... » read more

What’s Changing In SerDes
By Ed Sperling - 16 Apr, 2025 - Comments: 0

SerDes is all about pushing data through the smallest number of physical channels. But when it comes to AI, more data needs to be moved, and it has to be moved more quickly. Todd Bermensolo, product marketing manager at Alphawave Semi, talks about the impact of faster data movement on the transmitter (more power) and on the receiver (gain and advanced equalization), how to ensure signal inte... » read more

PCIe Over Optical: Transforming High-Speed Data Transmission
By David Kulansky - 29 Aug, 2024 - Comments: 0

With the rise in AI requiring new computing models and enhanced data transmission methods to cope, the necessity for innovative, high-performance, and low-latency connectivity solutions has never been more apparent. PCIe over Optical is set to play a key role in enabling the growth of AI, and here we examine some of the intricacies of PCIe over Optical to explore its implementation, challenges,... » read more

Overcoming Signal Integrity Challenges Of 112G Connections
By Cadence - 13 Mar, 2024 - Comments: 0

One of the big challenges with 112G SerDes (and, to a lesser extent, all SerDes) is handling signal integrity issues. In the worst case of a long-reach application, the signal starts at the transmitter on one chip, goes from the chip to the package, across a trace on a printed-circuit board (PCB), through a connector, then a cable or backplane, another connector, another PCB trace, another pack... » read more

DSP Techniques For High-Speed SerDes
By Ed Sperling - 23 Oct, 2023 - Comments: 0

Sensors everywhere, more connected devices, and the rollout of smart everything has created a flood of data. The question now is how to best handle all of that data, where to process it, and how to move it locally and to the outside network. Madhumita Sanyal, technical product manager at Synopsys, talks about the need for continuous performance improvements in SerDes, PCIe, NRZ, and PAM4, and w... » read more

Chiplets: Deep Dive Into Designing, Manufacturing, And Testing
By The SE Staff - 07 Aug, 2023 - Comments: 0

Chiplets are a disruptive technology. They change the way chips are designed, manufactured, tested, packaged, as well as the underlying business relationships and fundamentals. But they also open the door to vast new opportunities for existing chipmakers and startups to create highly customized components and systems for specific use cases and market segments. This LEGO-like approach sounds ... » read more

224G SerDes Trend and Solution
By Yang Zhang - 27 Jul, 2023 - Comments: 1

As an industry early mover to support the emerging 800G/1.6T networks, Cadence taped out the 224G-LR SerDes PHY IP on TSMC’s 3nm process at the beginning of the year and expects the silicon to arrive soon. The IP supports 1-225Gbps data rates with excellent BER at long reach (LR). The ever-increasing bandwidth requirement in hyperscale data centers is driving the rapid growth of high-speed I/... » read more

Evolution Of Equalization Techniques In High-Speed SerDes For Extended Reaches
By Madhumita Sanyal - 20 Jul, 2023 - Comments: 0

The relentless demand for massive amounts of data is accelerating the pace of high-performance computing (HPC) within the high-speed Ethernet realm. This escalation, in turn, intensified the complexity associated with designing networking SoCs, including switches, NICs, retimers, and pluggable modules. Such growth is accelerating the demand for bandwidth hungry applications to transition from 4... » read more

ESD Co-Design For High-Speed SerDeS In FinFET Technologies
By Synopsys - 07 Jun, 2023 - Comments: 0

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, including the phase from the completion of the silicon wafer processing to when the device (die) is assembled in the system. To avoid yield loss due to ESD damage during this early phase, on-chip ESD protection measures are applied to provide a certain degree of ESD robustness. The componen... » read more

Design Challenges Of High-Speed Wireline Transmitters
By Samad Parekh - 27 Apr, 2023 - Comments: 0

By Samad Parekh and Noman Hai The need for higher bandwidth networking equipment as well as connectivity in the cloud and hyperscale data centers is driving the switch technology transition from 25T (terabytes) to 50T and soon to 100T. The industry has chosen Ethernet to drive the switch market, using 112G SerDes technology today and next generation architectures being designed to operate at... » read more

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