tag: SerDes

The Challenges Of Designing 28G And 56G SerDes IP
By Jeff Kaady - 12 Jan, 2017 - Comments: 1

The industry move to 56 Gbps PAM4 is undoubtedly one of the greatest challenges currently facing SerDes IP designers and their customers. To begin with, shifting to 56 Gbps PAM4 immediately causes a loss of 9 dB. While the baud rate is 28 Gbaud, there are now three eyes stacked on top of each other. Nevertheless, there is still demand for 35+ dB reach. This is a significant challenge which requ... » read more

What’s Missing In Advanced Packaging
By Ann Mutschler - 22 Dec, 2016 - Comments: 0

Even though Moore's Law is running out of steam, there is still a need to increase functional density. Increasingly, this is being done with heterogeneous integration at the package or module level. This is proving harder than it looks. At this point there are no standardized methodologies, and tools often are retrofitted versions of existing tools that don't take into account the challenges... » read more

Chip Advances Play Big Role In Cloud
By Gale Morrison - 12 Dec, 2016 - Comments: 0

Semiconductor engineering teams have been collaborating with key players in the data center ecosystem in recent years, resulting in unforeseen and substantial changes in how data centers are architected and built. That includes everything from which boxes, boards, cards and cables go where, to how much it costs to run them. The result is that bedrock communication technology and standards li... » read more

Faster SerDes For More Efficient Data Centers
By Steven Woo - 10 Nov, 2016 - Comments: 0

The evolving data center presents an imposing set of challenges for system architects as Dennard Scaling fades and Moore’s Law wanes. These include an exponential increase in data, shifting architectural bottlenecks and a never-ending demand for higher performance within the same power and thermal envelopes. The Internet of Things (IoT), Big Data analytics, in-memory computing and machine ... » read more

Silicon Photonics Comes Into Focus
By Ed Sperling - 31 Oct, 2016 - Comments: 5

Silicon photonics is attracting growing attention and investment as a companion technology to copper wiring inside of data centers, raising new questions about what comes next and when. Light has always been the ultimate standard for speed. It requires less energy to move large quantities of data, generates less heat than electricity, and it can work equally well over long or short distances... » read more

Integration IP Helps IP Integration
By Brian Bailey - 08 Sep, 2016 - Comments: 0

You might not know much about the MIPI Alliance if you aren't designing mobile phones, but you will soon. Other application areas are taking interest in what this group has accomplished. The alliance was founded in 2003 to create standards for hardware and software interfaces in mobile devices. Successful examples include a camera serial interface (CSI) and a display serial interface (DSI), ... » read more

Why Use A Package?
By Ed Sperling - 21 Jan, 2016 - Comments: 0

Subramanian Iyer, distinguished chancellor's professor in UCLA's Electrical Engineering Department—and a former fellow and director of the systems scaling technology department at IBM—sat down with Semiconductor Engineering to talk about the future of chip scaling. What follows are excerpts of that conversation. SE: Advanced packaging is being viewed as a way to extend scaling in the fut... » read more

One PHY Does Not Fit All
By Rita Horner - 14 May, 2015 - Comments: 0

Consumers expect their battery-operated mobile devices to be faster, smaller and more reliable while providing greater functionality at a reduced cost. Most of all, consumers demand longer battery life and 24/7 access to data. To meet these demands, consumer system-on-a-chip (SoC) designers must make tradeoffs between features, performance, power and cost. Enterprise SoC designers have their... » read more

The Week In Review: Design
By Ed Sperling - 19 Sep, 2014 - Comments: 0

Tools Open-Silicon uncorked a 28Gbps SerDes evaluation platform, complete with board, test chip and characterization data, which it says will speed up and simplify development of chips for 100G networks. The chip utilizes PHY IP from Semtech. IP Synopsys rolled out MIPI C-PHY verification IP that utilizes a three-phase coding technique for faster camera, display and SoC interfaces. http://... » read more

The Week In Review: Design
By Ed Sperling - 08 Aug, 2014 - Comments: 0

Tools Cadence rolled out a custom power integrity tool for dealing with transistor-level electromigration and IR drop with SPICE-level accuracy. It works in conjunction with the company’s existing power integrity tool for cell-level power signoff. Open-Silicon established a high-speed SerDes technology center of excellence to speed design and production of ASICs using high-speed serial co... » read more

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