tag: shift left

Shifting Left With DFT To Optimize Productivity, Testability, And Time-To-Market
By Siemens EDA - 08 May, 2025 - Comments: 0

This paper discusses one of the Siemens EDA shift-left strategies in the RTL-to-signoff flow: shift-left design-for-test (DFT). Tessent RTL Pro software automates the analysis and insertion of Tessent VersaPoint test point technology, LBIST-OST test points, dedicated scan wrapper cells and x-bounding logic as behavioral code at the RTL level. Tessent RTL Pro builds on Tessent’s market-leading... » read more

Reap Rewards With Shift-Left Pattern Matching For Custom And AMS Designs
By John Muirhead - 24 Apr, 2025 - Comments: 0

To keep up with the growing complexities of IC design, major semiconductor companies are adopting shift-left strategies. For verification, this means pulling much of the work into the physical design stage. By moving critical checks earlier in the design cycle, you can identify and resolve issues before they escalate, streamlining the overall development process. The Calibre tools have been ... » read more

Shift Left In DFT Design
By Jeff Mayer - 08 Apr, 2025 - Comments: 0

The semiconductor industry continues to face numerous challenges as designs approach reticle limits, process nodes evolve and engineering resources become increasingly stretched. It is essential to maintain high productivity and quality throughout the design flow. This keeps projects on schedule, within budget, and ensures they remain high-quality, reliable, yield well and perform as intended. ... » read more

Shift-Left Pattern Matching Boosts Automotive IC Quality And Time-To-Market
By John Muirhead - 06 Mar, 2025 - Comments: 0

As the automotive industry races towards a future of connected, autonomous, and electrified vehicles, the complexity of integrated circuits (ICs) powering these innovations is reaching unprecedented levels. Modern automotive ICs incorporate a diverse mix of custom and third-party intellectual property (IP), each with unique performance requirements that must be meticulously verified to ensure f... » read more

Improving Verification Methodologies
By Brian Bailey - 27 Feb, 2025 - Comments: 0

Methodology improvements and automation are becoming pivotal for keeping pace with the growing complexity and breadth of the tasks assigned to verification teams, helping to compensate for lagging speed improvements in the tools. The problem with the tools is that many of them still run on single processor cores. Functional simulation, for example, cannot make use of an unlimited number of c... » read more

Controlling Leakage Power
By Matthew Hogan - 17 Feb, 2025 - Comments: 0

IC designers face a significant challenge in managing leakage power - a phenomenon that can profoundly impact your device's power, performance, area (PPA), and overall reliability. Leakage can occur in various ways, from parasitic leakage to analog gate leakage or digital gate leakage, and you must address these issues with great care, as even subtle circuit changes can lead to reliability prob... » read more

Enhancing Reliability For Automotive ICs
By Matthew Hogan - 06 Feb, 2025 - Comments: 0

As an IC designer focused on automotive applications, reliability is likely one of your top priorities. The components you develop need to withstand extreme environmental conditions, maintain performance over extended lifetimes, and meet rigorous industry standards. Failure is simply not an option when it comes to automotive electronics. Achieving the required levels of reliability can be a ... » read more

Tackling Reliability In Early IC Design
By Matthew Hogan - 09 Jan, 2025 - Comments: 0

As the semiconductor industry continues its relentless march towards smaller process nodes and more complex integrated circuits (ICs), the challenge of ensuring reliability has become increasingly difficult. Industry analysts predict a significant increase in demand for semiconductor reliability verification as analysis become critical parts of the overall design verification process. The st... » read more

Calibre DesignEnhancer Design-Stage Layout Modification Improves Power Management Faster And Earlier
By Siemens EDA - 20 Dec, 2024 - Comments: 0

In today’s IC designs, effective power management through layout optimization is crucial for achieving PPA targets. This paper, written by Jeff Wilson, describes how the Calibre DesignEnhancer platform, is used to specifically tackle the EMIR components of power management. DesignEnhancer offers P&R and custom/analog design teams a fast, integrated environment for implementing Calibre-cle... » read more

Enhancing Power Reliability Through Design-Stage Layout Optimization
By Jeff Wilson - 19 Dec, 2024 - Comments: 0

As integrated circuit (IC) designs continue to scale, the demand for efficient power management, performance optimization and reliable physical layout modification grows more critical. Meeting these power, performance and area (PPA) targets is essential for ensuring that IC designs operate effectively at advanced process nodes. One of the main challenges for design and verification engineers is... » read more

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