Week In Review: Design, Low Power


RISC-V RISC-V International announced four new specification and extension approvals. Efficient Trace for RISC-V defines an approach to processor tracing that uses a branch trace. RISC-V Supervisor Binary Interface architects a firmware layer between the hardware platform and the operating system kernel using an application binary interface in supervisor mode to enable common platform services... » read more

IC Reliability Burden Shifts Left


Chip reliability is coming under much tighter scrutiny as IC-driven systems take on increasingly critical and complex roles. So whether it's a stray alpha particle that flips a memory bit, or some long-dormant software bugs or latent hardware defects that suddenly cause problems, it's now up to the chip industry to prevent these problems in the first place, and solve them when they do arise. ... » read more

EDA Embraces Big Data Amid Talent Crunch


The semiconductor industry’s labor crunch finally has convinced chip designers to bet big money on big data. As recently as 2016, executives weren’t sure there was a market for big data approaches to electronic design automation. The following year, utilization of big data remained stuck in its infancy. And in 2018, Semiconductor Engineering questioned why the EDA sector wasn’t investi... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility U.S. National Highway Traffic Safety Administration (NHTSA) release its first crash reports from ADAS (advanced driver assistance systems, i.e., SAE Level 2) and ADS (automated driving systems, i.e., SAE Levels 3-5).  The systems had to be in use at least 30 seconds before the crash in order for it to be reportable. The car may have had the system turned off at the time ... » read more

Keeping IC Packages Cool


Placing multiple chips into a package side-by-side can alleviate thermal issues, but as companies dive further into die stacking and denser packaging to boost performance and reduce power, they are wrestling with a whole new set of heat-related issues. The shift to advanced packaging enables chipmakers to meet demands for increasing bandwidth, clock speeds, and power density for high perform... » read more

Week In Review: Design, Low Power


EnSilica listed on the London Stock Exchange's AIM market under the ticker ENSI. EnSilica designs mixed signal ASICs for system developers in the automotive, industrial, healthcare, and communications markets. It also has a portfolio of core IP covering cryptography, radar and communications systems. AIM is the LSE’s market for small and medium sized growth companies. "In connection with Admi... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility Cadence is now an official technology partner of the McLaren Formula 1 Team. The team will use Cadence’s Fidelity CFD Software to look at the computational fluid dynamics (CFD) of the airflow around the race cars and predict how a car design will affect the airflow. Infineon uncorked its XENSIV 60 GHz automotive radar sensor for in-cabin monitoring systems. One use ca... » read more

Week In Review: Design, Low Power


Cadence's digital full flow was certified for the GlobalFoundries 12LP/12LP+ process platforms. The certified tools include the Innovus Implementation System, Genus Synthesis Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Quantus Extraction Solution, Litho Physical Analyzer (LPA), and Pegasus Verification System. Siemens Digital Industries Software's Calibre nm... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility The number new energy vehicles (NEVs) sold went up 80% from year over year, says TrendForce in its review of market for Q1 2022. NEVs are battery electric vehicles (BEVs), plug-in hybrid electric vehicles (PHEVs), and fuel cell vehicles. Over 2.004 million units sold in the first quarter of 2022 (1Q22), with BEVs making the strongest showing at 1.508 million units, a 271% ... » read more

Improving PPA With AI


AI/ML/DL is starting to show up in EDA tools for a variety of steps in the semiconductor design flow, many of them aimed at improving performance, reducing power, and speeding time to market by catching errors that humans might overlook. It's unlikely that complex SoCs, or heterogeneous integration in advanced packages, ever will be perfect at first silicon. Still, the number of common error... » read more

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