tag: Siemens EDA

No-Compromise Packetized Test Improves DFT Efforts
By Peter Orlando - 14 Jan, 2025 - Comments: 0

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test cost. The traditional method for evaluating these trade-offs has been to use hierarchical DFT methods in a divide-and-conquer approach. In hierarchical DFT efforts, all implementation, including pattern generation and verification, is done at the cor... » read more

DFT At The Leading Edge
By Gregory Haley - 14 Jan, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the rapidly changing landscape of design for testability (DFT), focusing on the impact of advancements in fault models, high-speed interfaces, and lifecycle data analytics, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; D... » read more

Startup Challenges In A Changing EDA World
By Brian Bailey - 13 Jan, 2025 - Comments: 0

The Electronic Design Automation (EDA) industry is a mature industry, but it's also one that is constantly changing. Each process node and packaging technology advancement places new demands and constraints on existing tools. In addition, changing design problems and paradigms transform how design teams operate, and the goals they target. For a relatively small industry, EDA requires a dispr... » read more

Edge And IoT Security Turning A Corner
By Ed Sperling - 09 Jan, 2025 - Comments: 0

Security is beginning to improve for a wide range of IoT and edge devices due to better tools, the implementation of new standards and methodologies, and an increasing level of collaboration and communication across different market segments that in the past had little or no interaction. Until recently, many vendors in cost-sensitive markets offered the bare minimum of security. To make matt... » read more

ISO 26262’s Importance Widens Beyond Automotive
By Adam Kovac - 09 Jan, 2025 - Comments: 0

The ISO 26262 standard, which has become a mainstay since the trend toward vehicle electrification really took root a decade ago, is starting to gain traction in markets outside of automotive chip and system design. At the center of this expansion is a focus on safety under a variety of conditions — extreme temperatures, unexpected vibration, or a collision that is unavoidable. This includ... » read more

Averting Hacks Of PCIe Transport Using CMA/SPDM
By Siemens EDA - 09 Jan, 2025 - Comments: 0

This paper describes the component measurement and authentication (CMA) and security protocol and data model (SPDM) flow used to establish the secure channels required for the transmission of encrypted packets. The various approaches, namely the symmetric and asymmetric flows, will be discussed in establishing a secure connection with the implementation of CMA/SPDM packets through data objects.... » read more

Tackling Reliability In Early IC Design
By Matthew Hogan - 09 Jan, 2025 - Comments: 0

As the semiconductor industry continues its relentless march towards smaller process nodes and more complex integrated circuits (ICs), the challenge of ensuring reliability has become increasingly difficult. Industry analysts predict a significant increase in demand for semiconductor reliability verification as analysis become critical parts of the overall design verification process. The st... » read more

Blog Review: Jan. 8
By Jesse Allen - 08 Jan, 2025 - Comments: 0

Cadence's Igor Krause unravels the different Orthogonal Header Content (OHC) types in PCIe 6.0, which work as an extra header for the Transaction Layer Packet (TLP) that incorporates information fields that are needed depending on the TLP type. Siemens EDA's Yunhong Min considers how AI and machine learning are reshaping functional verification workflows from translating specifications to de... » read more

Calibre DesignEnhancer Design-Stage Layout Modification Improves Power Management Faster And Earlier
By Siemens EDA - 20 Dec, 2024 - Comments: 0

In today’s IC designs, effective power management through layout optimization is crucial for achieving PPA targets. This paper, written by Jeff Wilson, describes how the Calibre DesignEnhancer platform, is used to specifically tackle the EMIR components of power management. DesignEnhancer offers P&R and custom/analog design teams a fast, integrated environment for implementing Calibre-cle... » read more

Strain, Stress In Advanced Packages Drives New Design Approaches
By Ann Mutschler - 19 Dec, 2024 - Comments: 2

Thermal and mechanical stresses are creating significant challenges in heterogeneous chiplet assemblies, increasing the time and cost required to work through all the possible physical effects, dependencies, and interactions, and driving demand for new tools. Unlike in the past, when various components were crammed into a planar SoC on a relatively thick substrate, the new substrates are bei... » read more

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