tag: Siemens EDA

Hunting For Hardware-Related Errors In Data Centers
By Anne Meixner - 07 Feb, 2023 - Comments: 2

The semiconductor industry is urgently pursuing design, monitoring, and testing strategies to help identify and eliminate hardware defects that can cause catastrophic errors. Corrupt execution errors, also known as silent data errors, cannot be fully isolated at test — even with system-level testing — because they occur only under specific conditions. To sort out the environmental condit... » read more

Bump Reliability is Challenged By Latent Defects
By Karen Heyman - 07 Feb, 2023 - Comments: 0

Thermal stress is a well-known problem in advanced packaging, along with the challenges of mechanical stress. Both are exacerbated by heterogenous integration, which often requires mingling materials with incompatible coefficients of thermal expansion (CTE). Effects are already showing up and will likely only get worse as package densities increase beyond 1,000 bumps per chip. “You comb... » read more

Ramping Up IC Predictive Maintenance
By Anne Meixner - 07 Feb, 2023 - Comments: 0

The chip industry is starting to add technology that can predict impending failures early enough to stave off serious problems, both in manufacturing and in the field. Engineers increasingly are employing in-circuit monitors embedded in SoC designs to catch device failures earlier in the production flow. But for ICs in the field, data tracing from design to application use only recently has ... » read more

Week in Review: Design, Low Power
By Jesse Allen - 03 Feb, 2023 - Comments: 0

Intel discontinued its Pathfinder for RISC-V program, according to numerous reports. The program provided a pre-silicon development environment to support IP selection and early-stage software development using Intel FPGA and simulator platforms. "Since Intel will not be providing any additional releases or bug fixes, we encourage you to promptly transition to third-party RISC-V software tools ... » read more

A New Era In Requirements Management
By Jacob Wiltgen - 02 Feb, 2023 - Comments: 0

Project teams face a host of challenges when developing semiconductors compliant to a safety critical market. ISO 26262 drives state-of-the art safety critical designs for automotive electronics, DO-254 for airborne electronics hardware, and IEC61508 for industrial electronics, to name a few. In the context of ISO 26262, much of the discussion in recent years has been on challenges addressin... » read more

Intelligent Traceability For ISO 26262
By Siemens EDA - 01 Feb, 2023 - Comments: 0

Requirements driven development is a foundational component of any safety critical lifecycle, including ISO 26262, the state-of-the-art standard guiding safety in the development of automotive electronic devices. At face value, requirements seem like a very straight forward concept. Project teams write requirements. Requirements are implemented into the product. The product is tested... » read more

Blog Review: Feb. 1
By Jesse Allen - 01 Feb, 2023 - Comments: 0

Siemens EDA's Harry Foster explores trends in low power design techniques for ICs and ASICs, with 72% of design projects reported actively managing power. Synopsys' Charlie Matar, Rita Horner, and Pawini Mahajan look at the concept of reliability, availability, and serviceability (RAS) in the context of high-performance computing SoC designs and how it can be supported with silicon lifecycle... » read more

Power Issues Causing More Respins At 7nm And Below
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Power consumption has been a major design consideration for some time, but it is far from being a solved issue. In fact, an increasing number of designs have a plethora of power-related problems, and those problems are getting worse in new chip designs. Many designs today are power-limited — or perhaps more accurately stated, thermal-limited. A chip only can consume as much power as it is ... » read more

The QA Exchange Deck In Solido Crosscheck Enables An IP Qualification Handshake
By Siemens EDA - 26 Jan, 2023 - Comments: 0

This paper describes how the QA exchange deck in Siemens EDA’s Solido Crosscheck software can be used to capture and exchange IP qualification requirements. It shows how the QA exchange deck can be used as part of the IP validation framework in Solido Crosscheck to provide an IP signoff handshake between IP suppliers and integrators. To read more, click here. » read more

Blog Review: Jan. 25
By Jesse Allen - 25 Jan, 2023 - Comments: 0

Cadence's Shyam Sharma shares some important design and verification considerations when working with DDR5 SDRAM and DDR5 DIMM-based memory subsystems, including reset and power on initialization, speed bin compliance, and refresh, RFM, and temperature requirements. Siemens EDA's Harry Foster examines trends in adoption of languages and libraries for IC and ASIC design, testbench creation, a... » read more

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