tag: Siemens EDA

Blog Review: Dec. 20
By Jesse Allen - 20 Dec, 2022 - Comments: 0

Synopsys' Twan Korthorst explains how PDKs can help accelerate the photonic IC design process by offering building blocks such as several types of waveguides, passive devices like splitters, combiners, and filters, along with active devices such as phase shifters, detectors, semiconductor optical amplifiers, and lasers. Siemens EDA's Harry Foster examines IC and ASIC design trends, including... » read more

Efficient Trace In RISC-V
By Ed Sperling - 19 Dec, 2022 - Comments: 0

Systems with RISC-V cores often include multiple types of other processors and accelerators. Peter Shields, product manager for Tessent at Siemens Digital Industries Software, talks about what's needed for debug and trace in context, including the need for unobtrusive observation at full speed, what to trace and when to trace it, and how embedded IP can identify to report which branches are tak... » read more

The March Toward Chiplets
By Ed Sperling and Karen Heyman - 15 Dec, 2022 - Comments: 0

The days of monolithic chips developed at the most advanced process nodes are rapidly dwindling. Nearly everyone working at the leading edge of design is looking toward some type of advanced packaging using discrete heterogeneous components. The challenge now is how to shift the whole chip industry into this disaggregated model. It's going to take time, effort, as well as a substantial reali... » read more

3D-IC Reliability Degrades With Increasing Temperature
By Ann Mutschler - 14 Dec, 2022 - Comments: 0

The reliability of 3D-IC designs is dependent upon the ability of engineering teams to control heat, which can significantly degrade performance and accelerate circuit aging. While heat has been problematic in semiconductor design since at least 28nm, it is much more challenging to deal with inside a 3D package, where electromigration can spread to multiple chips on multiple levels. “Be... » read more

Blog Review: Dec. 14
By Jesse Allen - 14 Dec, 2022 - Comments: 0

Siemens EDA's Harry Foster checks out design and verification language adoption trends in FPGA projects, including testbench methodologies and assertion languages. Cadence's Veena Parthan finds that giving electric vehicle batteries a second life as energy storage devices can extend their useful life by 5 to 8 years, but a lack of standardization in EV batteries poses challenges. Synopsys... » read more

Variability Becoming More Problematic, More Diverse
By Karen Heyman - 12 Dec, 2022 - Comments: 0

Process variability is becoming more problematic as transistor density increases, both in planar chips and in heterogeneous advanced packages. On the basis of sheer numbers, there are many more things that can wrong. “If you have a chip with 50 billion transistors, then there are 50 places where a one-in-a-billion event can happen,” said Rob Aitken, a Synopsys fellow. And if Intel’s... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Dec, 2022 - Comments: 0

Tools, IP, design Codasip launched a new organization within the company to support the development and commercialization of technical innovations in key applications including security, functional safety, and AI/ML. "As semiconductor scaling is showing its limits, there is an obvious need for new ways of thinking. We will be working with universities, research institutes and strategic partner... » read more

Ready, Set, Go: Outrunning Moore’s Law With 3D-IC
By Tony Mastroianni - 08 Dec, 2022 - Comments: 0

By Anthony Mastroianni and Gordon Allan, Siemens EDA 3D ICs are an exciting and promising extension of heterogeneous advanced package technology into the third dimension. Although far from mainstream, 3D IC’s time is coming, as chiplet standardization efforts and supporting tool developments begin to make 3D IC practicable and profitable to more players – big and small – and products w... » read more

IC Stresses Affect Reliability At Advanced Nodes
By Ann Mutschler - 08 Dec, 2022 - Comments: 1

Thermal-induced stress is now one of the leading causes of transistor failures, and it is becoming a top focus for chipmakers as more and different kinds of chips and materials are packaged together for safety- and mission-critical applications. The causes of stress are numerous. In heterogeneous packages, it can stem from multiple components composed of different materials. “These materia... » read more

Challenges With Adaptive Control
By Brian Bailey - 08 Dec, 2022 - Comments: 0

Historically, the performance and power consumption of a system was controlled by what could be done at design time, but chips today are becoming a lot more adaptive. This has become a necessity for cutting edge nodes, but also provides a lot of additional benefits at the expense of greater complexity and verification challenges. Design margins are a tradeoff between performance and yield. C... » read more

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