tag: Siemens EDA

Shift Left, Extend Right, Stretch Sideways
By Brian Bailey - 27 Jul, 2023 - Comments: 0

The EDA industry has been talking about shift left for a few years, but development flows are now being stretched in two additional ways, extending right to include silicon lifecycle management, and sideways to include safety and security. In addition, safety and security join verification and power as being vertical concerns, and we are increasingly seeing interlinking within those concerns. ... » read more

Context-Aware Analysis Can Automatically Protect Critical Nets And Devices During Fill Insertion
By Dina Medhat - 27 Jul, 2023 - Comments: 0

Context-aware physical verification (PV) is a relatively new addition to traditional PV flows, but it has quickly become a critical and essential technology that addresses the increasing complexity of geometrical checks used in both established and emerging integrated circuit (IC) technologies. Traditional electronic design automation (EDA) verification tools handle either the physical verifica... » read more

Placement And CTS Techniques For High-Performance Computing Designs
By Siemens EDA - 26 Jul, 2023 - Comments: 0

This paper discusses the challenges of designing high-performance computing (HPC) integrated circuits (ICs) to achieve maximum performance. The design process for HPC ICs has become more complex with each new process technology, requiring new architectures and transistors. We highlight how the Siemens Aprisa digital implementation solution can solve placement and clock tree challenges in HPC de... » read more

Blog Review: July 26
By Jesse Allen - 26 Jul, 2023 - Comments: 0

Siemens' Chris Spear shows how to make a group of specialized classes in SystemVerilog. Synopsys' Guy Cortez and Randy Fish consider what a silicon lifecycle management strategy looks like for SoCs deployed in HPC and data center environments. Cadence's Veena Parthan provides a primer on writing Python scripts for Fidelity, including API descriptions and different sets of packages to acce... » read more

Getting Rid Of Heat In Chips
By Brian Bailey - 20 Jul, 2023 - Comments: 1

Power consumed by semiconductors creates heat, which must be removed from the device, but how to do this efficiently is a growing challenge. Heat is the waste product of semiconductors. It is produced when power is dissipated in devices and along wires. Power is consumed when devices switch, meaning that it is dependent upon activity, and that power is constantly being wasted by imperfect de... » read more

A New Approach To Design-Stage Layout Optimization Can Speed Time To Tapeout While Improving Power Management
By Jeff Wilson - 20 Jul, 2023 - Comments: 0

The right tool for the job makes all the difference. Ever try hammering a nail in with a rock? How many nails did you ruin before you gave up? Or try to tighten a crucial bolt by hand? It takes forever, and you just can’t tighten it enough, so everything’s still kind of wobbly? Yeah, that’s kind of what it’s like trying to use an electronic design automation (EDA) tool to do a job it’... » read more

Calibre DesignEnhancer Design-Stage Layout Modification Improves Power Management Faster And Earlier
By Siemens EDA - 19 Jul, 2023 - Comments: 0

The faster a design can progress from implementation to signoff verification, the better the chances are of meeting tapeout schedules. The Calibre DesignEnhancer platform offers P&R and custom/analog design teams a fast, integrated environment for implementing Calibre-clean design modifications to reduce IR drop and EM and prepare for physical verification. Not only can designers reduce EM and ... » read more

Blog Review: July 19
By Jesse Allen - 19 Jul, 2023 - Comments: 0

Siemens' Keith Felton argues that co-design-driven semiconductor package planning and prototyping is critical for design success and points to how interchange formats enable designers to make trade-off decisions for both the package and the board and communicate those recommendations back to the other design team in formats that are native to their tools. Cadence's Xin Mu explains precoding ... » read more

Week In Review: Semiconductor Manufacturing, Test
By Gregory Haley - 14 Jul, 2023 - Comments: 0

SEMICON West returned in force this week, with a focus on AI and deep learning  in semiconductor manufacturing, security, heterogenous ICs, and the march toward a $1 trillion chip market. Lam Research President and CEO, Tim Archer, opened with the keynote presentation. Fig. 1: SEMICON West panel: AI’s influence on growth, China-U.S. trade war, and the importance of climate policy were... » read more

Week In Review: Design, Low Power
By SE Staff - 14 Jul, 2023 - Comments: 0

DAC and SEMICON WEST rebounded this year, focusing on everything from security to chiplets and smart manufacturing. Panel at DAC conference: Left to right, ARM’s Brian Fuller (moderator), Joe Costello (Metrics, Kwikbit, Arrikto, Acromove), and Wally Rhines (Cornami). Source: Semiconductor Engineering/Ann Mutschler EDA and IP remain strong, approaching $4 billion in Q1, according to ... » read more

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