tag: Siemens EDA

12 Ways To Elevate Electronic Design Process Using PADS eBook
By Siemens EDA - 07 Dec, 2022 - Comments: 0

When using PADS Professional Premium, designers have access to standard PCB design functionality, such as schematic definition and physical layout, as well previously optional add-on features (now standard) and all of the latest cloud apps, including: Schematic definition: Access to everything you need: Circuit design and simulation, Component selection, library management, and signal integr... » read more

Blog Review: Dec. 7
By Jesse Allen - 07 Dec, 2022 - Comments: 0

Siemens EDA's Harry Foster looks at the continual maturing of FPGA functional verification processes through increasing adoption of various simulation-based and formal verification techniques. Synopsys' Stewart Williams introduces the Scalable Open Architecture for Embedded Edge (SOAFEE) project and how it can make automotive software development, testing, virtual prototyping, and validation... » read more

Systematic Yield Issues Now Top Priority At Advanced Nodes
By Laura Peters - 06 Dec, 2022 - Comments: 0

Systematic yield issues are supplanting random defects as the dominant concern in semiconductor manufacturing at the most advanced process nodes, requiring more time, effort, and cost to achieve sufficient yield. Yield is the ultimate hush hush topic in semiconductor manufacturing, but it's also the most critical because it determines how many chips can be profitably sold. "At older nodes, b... » read more

Adopting Predictive Maintenance On Fab Tools
By Anne Meixner - 06 Dec, 2022 - Comments: 0

Predictive maintenance, based on more and better sensor data from semiconductor manufacturing equipment, can reduce downtime in the fab and ultimately cut costs compared with regularly scheduled maintenance. But implementing this approach is non-trivial, and it can be disruptive to well-honed processes and flows. Not performing maintenance quickly enough can result in damage to wafers or the... » read more

Manage Your Risk In RISC-V
By Peter Shields - 06 Dec, 2022 - Comments: 0

Adoption of RISC-V processors is accelerating. This technology, like everything, comes with benefits and risks. The open standard means freedom for many developers, but success depends on the development of a support ecosystem around RISC-V. Industry collaboration is making broad adoption of RISC-V possible, and one example is the introduction of efficient trace for RISC-V cores. When incorp... » read more

Packetized Scan Test
By Siemens EDA - 06 Dec, 2022 - Comments: 0

Bus-based packetized scan data decouples test delivery and core-level DFT requirements so core-level compression configuration can be defined completely independently of chip I/O limitations. Grouping cores for concurrent testing is selected programmatically, not hard-wired. This concept dramatically reduces the DFT planning and implementation effort. The Siemens solution for packetized deli... » read more

Peeling The Onion Of An Automotive IC Digital Twin
By Siemens EDA - 01 Dec, 2022 - Comments: 0

This paper defines the modern digital twin in the context of the automotive industry and as it applies to the ICs being deployed therein. Additionally, it surveys the implications arising from the need to use digital twins to connect the virtual and physical worlds for semiconductor suppliers delivering the next generation of automotive capabilities. Why should I care about digital twins? T... » read more

Blog Review: Nov. 30
By Jesse Allen - 30 Nov, 2022 - Comments: 0

Cadence's Sangeeta Soni explores how the configuration space for CXL 1.1 and CXL 2.0 varies and discusses newly introduced registers for the CXL-compliant devices and how they are discovered during the CXL enumeration flow. Siemens EDA's Harry Foster continues examining trends in FPGA verification effort by looking at where both design and verification engineers spend their time. Synopsys... » read more

Improving Concurrent Chip Design, Manufacturing, And Test Flows
By Ann Mutschler - 28 Nov, 2022 - Comments: 0

Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale. The glue between these various processes is data, and the chip industry is working to weave together various steps t... » read more

An Organic Package Designer’s Guide To Transitioning To FOWLP And 2.5D Design
By Siemens EDA - 23 Nov, 2022 - Comments: 0

The IC packaging design tool set has matured to the point where it can address not only classic plastic, organic and ceramic packaging substrates but can also address silicon substrates driven by interposer and chiplet designs. In most cases system and packaging teams do not have to abandon their existing tool set to support these designs. In fact, the packaging design tool set can offer additi... » read more

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