tag: Siemens

Blog Review: Dec. 30
By Jesse Allen - 30 Dec, 2020 - Comments: 0

Cadence's Paul McLellan considers what the next ten years will look like for the RISC-V ISA with an expanding software ecosystem and increasing number of commercial and open cores available. Siemens EDA's Harry Foster checks out the languages and libraries being used to design and verify FPGAs and how they've changed over the last several years. Synopsys' Jonathan Knudsen contends that IT... » read more

2020: A Turning Point In The Chip Industry
By Brian Bailey - 28 Dec, 2020 - Comments: 3

At the start of 2020, most of the industry was upbeat and sales forecasts for the year were good. Then the pandemic hit, and fear gripped most of the industry — but not for long. New markets emerged, demand increased, and the levels of innovation went far beyond what had been forecast. While hope is on the horizon that the virus will be contained during 2021, life will not return to the ol... » read more

Blog Review: Dec. 23
By Jesse Allen - 23 Dec, 2020 - Comments: 0

Cadence's Paul McLellan checks out how Arm is becoming a powerhouse in the server and high-end space with the addition of new R&D and a focus on getting the most out of its architecture. Siemens EDA's Harry Foster continues his look at verification trends in FPGAs by checking out adoption of different simulation and formal technologies. Synopsys' Taylor Armerding looks ahead to 2021 w... » read more

RISC-V Verification Challenges Spread
By Ann Mutschler - 22 Dec, 2020 - Comments: 0

The RISC-V ecosystem is struggling to keep pace with rapid innovation and customization, which is increasing the amount of verification work required for each design and spreading that work out across more engineers at more companies. The historical assumption is that verification represents 60% to 80% or more of SoC project effort in terms of cost and time for a mature, mainstream processor... » read more

Stretching Engineers
By Brian Bailey - 22 Dec, 2020 - Comments: 1

Engineering has one constant — you innovate or fall by the wayside. That is true both for the things that are designed and for the engineers who design and build them. Today’s systems are putting new strains on engineers who can no longer be "tall and thin" or "short and fat." Those descriptions pertain to an engineer who is either highly specialized or one who has much broader experience. ... » read more

Optimizing Tool Integration Is Essential To Design Success
By James Paris - 22 Dec, 2020 - Comments: 0

By James Paris and Armen Asatryan The relationship between a place and route (P&R) application and the collection of system-on-chip (SoC) design implementation, analysis, and verification methodologies and tools has always been very much a two-way street. The P&R system is the base, if you will, of design implementation—it takes the virtual and makes it physical. However, it is use... » read more

Multicore Debug Evolves To The System-Level
By Ann Mutschler - 22 Dec, 2020 - Comments: 0

The proliferation and expansion of multicore architectures is making debug much more difficult and time-consuming, which in turn is increasing demand for more comprehensive system-level tools and approaches. Multicore/multiprocessor designs are the most complex devices to debug. More interactions and interdependencies between cores mean more things possibly can go wrong. In fact, so many pro... » read more

Week In Review: Design, Low Power
By Jesse Allen - 18 Dec, 2020 - Comments: 0

Tools, Cloud, IP Valtrix Systems updated its STING design verification tool for RISC-V based CPU and SoC implementations. Version 1.9.0 adds support to verify recent changes to the RISC-V user and privilege specifications, including draft versions of the vector and bit manipulation standard extensions. Preliminary support for the draft version of the RISC-V hypervisor extension has also been a... » read more

Blog Review: Dec. 16
By Jesse Allen - 16 Dec, 2020 - Comments: 0

Arm's Benoit Labbe investigates why battery monitoring is so important for a low-power microcontroller and shows how it was implemented in the M0N0 MCU while drawing a fraction of a nW in typical conditions. Siemens EDA's Harry Foster takes a look at how much of their time FPGA design engineers spend on verification, and the tasks that keep verification engineers the busiest. Synopsys' Sc... » read more

Fast, Low-Power Inferencing
By Russell Klein - 10 Dec, 2020 - Comments: 1

Power and performance are often thought of as opposing goals, opposite sides of the same coin if you will. A system can be run really fast, but it will burn a lot of power. Ease up on the accelerator and power consumption goes down, but so does performance. Optimizing for both power and performance is challenging. Inferencing algorithms for Convolutional Neural Networks (CNN) are compute int... » read more

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