Week In Review: Design, Low Power

Signal and power integrity analysis; PCIe 6.0 IP; cost-optimized, compact FPGA.


Qualcomm finalized its acquisition of data center chip startup Nuvia with a price of $1.4 billion. Nuvia is working on a data center SoC and Arm-based CPU core it claims will lower performance per total cost of ownership by matching high performance with high efficiency and limiting maximum power to that which can be dissipated in an air-cooled environment. Qualcomm said Nuvia’s technology would be incorporated into its portfolio of products, including the Snapdragon platform. Founded in 2019, Nuvia raised a $240 million Series B investment in September. The company was founded by former SoC and CPU architects from Apple and Google. It is based in Santa Clara, Calif.

Tools & IP
Cadence unveiled the Sigrity X signal and power integrity (SI/PI) tool suite. Sigrity X features new simulation engines for system-level analysis and includes the massively distributed architecture of the Clarity 3D Solver, providing up to a 10X performance gain for simulation speed and design capacity. It also has a new user experience that streamlines setup time for detailed system-level SI/PI analysis by transitioning seamlessly across different analysis workflows. MediaTek, Renesas, Samsung Electronics, and H3C Semiconductor Technologies noted adopting the tool.

Synopsys debuted DesignWare PCIe 6.0 IP that includes controller, PHY, and verification IP. Built on the DesignWare IP for PCIe 5.0, it supports the latest features in the standard specification including 64 GT/s PAM-4 signaling, FLIT mode, and L0p power state. The controller utilizes a MultiStream architecture, delivering up to 2X the performance of a single-stream design, and provides optimal flow with multiple data sources and in multi-virtual channel implementations. The PHY has a placement-aware architecture to minimize package crosstalk and provides adaptive DSP algorithms that optimize analog and digital equalization to maximize power efficiency regardless of the channel. Intel noted that the IP sets the stage for PCIe Gen 6 development and adoption on future platforms.

Xilinx expanded its UltraScale+ FPGA portfolio, adding smaller form factors for ultra-compact and edge applications. The cost-optimized 16nm Artix and Zynq UltraScale+ devices are available in TSMC’s InFO (Integrated Fan-Out) packaging technology. The Artix family targets applications such as machine vision with advanced sensor technology, high-speed networking, and ultra-compact “8K-ready” video broadcasting. In the Zynq family, the ZU1 is designed for connectivity at the edge and for industrial and healthcare IoT systems, including embedded vision cameras, AV-over-IP 4K and 8K-ready streaming, hand-held test equipment, as well as consumer and medical applications.

Siemens Digital Industries’ Veloce Network (VN) App was certified for use with the Keysight IxVerify 3.0 software pre-silicon test solution. The integration takes advantage of the high-performance co-model channel bandwidth of Veloce Strato emulation hardware together with the virtual IxVerify-VN App solution for deterministic, full-system verification and enables mutual Ethernet networking customers to accelerate their lab-based validation infrastructure using a pre-silicon environment on emulation hardware.

Arasan Chip Systems launched MIPI C-PHY/ D-PHY Combo IP compliant with the latest MIPI C-PHY v2.0 and MIPI D-PHY v2.5 specifications. It provides 6 Gbps per lane for a max throughput of 24 Gbps in D-PHY mode and 6 Gbps per trio for a max throughput of 41 Gbps in C-PHY mode.

Rockley Photonics adopted tools from Synopsys’ Photonic Solutions platform, including OptoCompiler, OptoDesigner, OptSim Circuit, RSoft Photonic Device Tools, and IC Validator. Rockley plans to use the tools to design and optimize photonic devices, create process design kits (PDKs) and tape out photonic ICs. “The PDA platform Rockley has created by utilizing OptoCompiler allows our engineers to define, simulate, lay out and verify Photonic ICs quickly and efficiently to meet our quality and schedule goals,” said Andrew Rickman, chief executive at Rockley.

The Open RF Association and the MIPI Alliance will be cooperating on joint collaborative projects relating to radio frequency front-end architecture, design, and technology. In particular, the OpenRF Register Map Working Group is creating a register map framework to maximize configurability and effectiveness of the RF front end. “The MIPI RFFE specification has become the de facto interface for control of the radio frequency front end since its release in 2010, and this specification will serve as a key component of our OpenRF Register Map templates,” said Kevin Schoenrock, President, Open RF Association. “We look forward to working with the MIPI Alliance to help optimize the RF front end and to support the growing 5G device ecosystem.”

Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

The Silicon Valley Women in Engineering Conference will be held Mar. 20. IRPS 2021: International Reliability Physics Symposium will be held Mar. 21-24, and the tinyML Summit: Enabling Ultra-low Power Machine Learning At The Edge will take place Mar. 22-26. The Leti Photonics Workshop will happen on Mar. 25 with multiple times available. The U.S. government-focused electronics conference GOMACTech will be held Mar. 29-Apr. 1.

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