New Architectures, Much Faster Chips


The chip industry is making progress in multiple physical dimensions and with multiple architectural approaches, setting the stage for huge performance increases based on more modular and heterogeneous designs, new advanced packaging options, and continued scaling of digital logic for at least a couple more process nodes. A number of these changes have been discussed in recent conferences. I... » read more

Challenges In Using AI In Verification


Pressure to use AI/ML techniques in design and verification is growing as the amount of data generated from complex chips continues to explode, but how to begin building those capabilities into tools, flows and methodologies isn't always obvious. For starters, there is debate about whether the data needs to be better understood before those techniques are used, or whether it's best to figure... » read more

The Evolution Of High-Level Synthesis


High-level synthesis is getting yet another chance to shine, this time from new markets and new technology nodes. But it's still unclear how fully this technology will be used. Despite gains, it remains unlikely to replace the incumbent RTL design methodology for most of the chip, as originally expected. Seen as the foundational technology for the next generation of EDA companies around the ... » read more

Radio Frequency Technology Is Found Everywhere In Daily Life


By Greg Curtis and YuLing Lin Innovation is everywhere around us. From high-performance computing, communications, autonomous driving, and the Internet of Things (figure 1), each segment has led to a rapid increase in design innovation. This innovation has been particularly true in communications, as Radio Frequency (RF) technology is found everywhere in daily life. RF technology is critical... » read more

Accelerate Time To Market With Calibre nmLVS-Recon Technology


One thing is clear…tapeouts are getting harder, and taking longer. As part of a growing suite of innovative early-stage design verification technologies, the Calibre nmLVS-Recon tool enables design teams to rapidly examine dirty and immature designs to find and fix high-impact circuit errors earlier and faster, leading to an overall reduction in tapeout schedules and time to market. To rea... » read more

Monitoring Chips After Manufacturing


New regulations and variability of advanced process nodes are forcing chip designers to insert additional capabilities in silicon to help with comprehension, debug, analytics, safety, security, and design optimization. The impact of this will be far-reaching as the industry discusses what capabilities can be shared between these divergent tasks, the amount of silicon area to dedicate to it, ... » read more

Blog Review: Aug. 19


Rambus' Scott Best digs into some of the most sophisticated attacks used to target and compromise security chips, such as laser voltage probing, focused ion beam editing, reverse engineering, and NVM extraction, and ways to counter them. Synopsys' Chris Clark proposes a way to identify problems earlier and better ensure safety and reliability in automotive SoCs by moving from a linear develo... » read more

From Cloud To Cloudlets


Cloudlets, or mini-clouds, are starting to roll out closer to the sources of data in an effort to reduce latency and improve overall processing performance. But as this approach gains steam, it also is creating some new challenges involving data distribution, storage and security. The growing popularity of distributed clouds is a recognition that the cloud model has limitations. Sending the ... » read more

How UVM Callbacks Simplify Assertion Validation


By Akshay Sarup and Mark Olen Assertions bring immediate benefits to the whole design and verification cycle; thus any challenges engineers face in coding and testing them are worth resolving. When a large number of assertions are to be validated, callbacks save time by eliminating the need to code a new sequence for each scenario. Callbacks also provide more dynamic and fine-grained cont... » read more

Preparing For A Barrage Of Physical Effects


Advancements in 3D transistors and packaging continue to enable better power and performance in a given footprint, but they also require more attention to physical effects stemming from both increased density and vertical stacking. Even in planar chips developed at 3nm, it will be more difficult to build both thin and thick oxide devices, which will have an impact on everything from power to... » read more

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