tag: signal integrity

Chiplets Add New Power Issues
By Ann Mutschler - 13 Mar, 2025 - Comments: 0

Delivering and managing power are becoming key challenges in the rollout of chiplets, adding significantly to design complexity and forcing chipmakers to weigh tradeoffs that can have a big impact on the performance, reliability, and the overall cost of semiconductors. Power is a concern for every chip and chiplet design, even if the specifics differ based on the application. Systems vendors... » read more

Signal Integrity Plays Increasingly Critical Role In Chiplet Design
By Ann Mutschler - 13 Feb, 2025 - Comments: 1

Maintaining the quality and reliability of electrical signals as they travel through interconnects is proving to be much more challenging with chiplets and advanced packaging than in monolithic SoCs and PCBs. Signal integrity is a fundamental requirement for all chips and systems, but it becomes more difficult with chiplets due to reflections, loss, crosstalk, process variation, and various ... » read more

Chiplet Interconnects Add Power And Signal Integrity Issues
By Adam Kovac - 12 Dec, 2024 - Comments: 0

The flexibility and scalability offered by chiplets make them an increasingly attractive choice over planar SoCs, but the rollout of increasingly heterogeneous assemblies adds a variety of new challenges around the processing and movement of data. Nearly all of the chiplets in use today were designed in-house by large systems companies and IDMs. Going forward, third-party chiplets will begin... » read more

Balancing Parallel Test Productivity With Yield & Cost
By Anne Meixner - 12 Nov, 2024 - Comments: 0

Parallel test is used for nearly every device produced by fabs and OSATs, but it can reduce yield and increase the cost of test boards and operations. This is a well-understood tradeoff for ensuring consistent test accuracy across multiple sites and reducing test time. Collectively, ATEs and multi-site test boards — DUT interface boards (DIBs), probe cards, and load boards — significantl... » read more

Managing Reflections With Terminations
By John Golding - 04 Nov, 2024 - Comments: 0

Have you heard recommendations to use a particular termination in particular situations for good signal integrity? Have you ever wondered how to incorporate terminations in your design? While there are typical use cases for various terminations, sometimes engineers use termination techniques based on a recommendation or assumption that may not work, or at least may not be optimal, for their par... » read more

Data Routing In Heterogeneous Chip Designs
By Ed Sperling - 30 Sep, 2024 - Comments: 0

Ensuring data gets to where it's supposed to go at exactly the right time is a growing challenge for design engineers and architects developing heterogeneous systems. There is more data moving around these chips with dozens of targets, which makes routing signals much more complicated. Ronen Perets, senior product marketing manager at Cadence Design Systems, talks about some of the new problems... » read more

Signal Integrity Basics
By Siemens EDA - 26 Sep, 2024 - Comments: 0

In this orientation to signal integrity basics, we aim to introduce several important and fundamental concepts of signal integrity for the beginner. Most explanations are provided at a high level without a lot of depth and math, and examples are provided with a focus on comparison rather than detailed numerical results. Of course, background depth, math, and numerical details are very important... » read more

Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization
By Cadence - 25 Sep, 2024 - Comments: 0

Abstract Over the past few decades, a lot of details have been worked out in power distribution network design, simulation and measurement. We have well-established PDN design procedures both in the frequency and time domains, we have simulation tools that can analyze the physical structure from DC to very high frequencies, including spatial variations of the behavior, and we also have fre... » read more

Managing EMI in High-Density Integration
By Gregory Haley - 19 Sep, 2024 - Comments: 0

The relentless drive for higher performance and increased functional integration has ushered in new challenges for managing electromagnetic interference (EMI) in densely packed mixed-signal environments. Integrating analog, RF, and digital circuits into a single system-on-chip (SoC) or advanced package requires solutions that reduce system size and improve performance. However, this tight in... » read more

Intel Vs. Samsung Vs. TSMC
By Ed Sperling - 15 Jul, 2024 - Comments: 3

The three leading-edge foundries — Intel, Samsung, and TSMC — have started filling in some key pieces in their roadmaps, adding aggressive delivery dates for future generations of chip technology and setting the stage for significant improvements in performance with faster delivery time for custom designs. Unlike in the past, when a single industry roadmap dictated how to get to the next... » read more

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