tag: silicon photonics

Important Changes Ahead
By Steve Schulz - 12 Jan, 2015 - Comments: 0

Two of Si2's important industry standards efforts will be featured later this month at DesignCon, a popular Silicon Valley event that is now in its 20th year. In the panel entitled, "System-Level Power Modeling—What's the Big Deal?", leading industry experts from AMD, Avago Technologies, Cadence, Docea Power, Qualcomm, and Si2 will focus on the growing need to take a higher level and more... » read more

System Bits: Oct. 28
By Ann Mutschler - 28 Oct, 2014 - Comments: 0

Sensing objects without looking at them In a technique known as “interaction-free measurement,” Yale engineers have created a chip-scale device that senses the presence of an object without interacting with it by using the wave-particle duality of single photons. This work could help propel the field of quantum information processing. The researchers explained that the device uses silic... » read more

The Week In Review: Design
By Ed Sperling - 19 Sep, 2014 - Comments: 0

Tools Open-Silicon uncorked a 28Gbps SerDes evaluation platform, complete with board, test chip and characterization data, which it says will speed up and simplify development of chips for 100G networks. The chip utilizes PHY IP from Semtech. IP Synopsys rolled out MIPI C-PHY verification IP that utilizes a three-phase coding technique for faster camera, display and SoC interfaces. http://... » read more

More Than Moore
By Ed Sperling - 15 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

Improving 2.5D Components
By Ed Sperling - 07 Aug, 2014 - Comments: 1

A lot of attention is being focused on improving designs at established, well-tested nodes where processes are mature, yields are high, and costs are under control. So what does this mean to stacking die? For 2.5D architectures, plenty. For 3D, probably not much. Here’s why: The advantage of 2.5D is that it can utilize dies created at whatever node makes sense. While the initial discuss... » read more

Disruptive R&D
By Paula Doe - 17 Jul, 2014 - Comments: 0

Leading university researchers presented their most promising technologies — describing developments ranging from sustainable metal cluster technology (that’s already spawned three notable startups) to resonance-based detection for more accurate MEMS devices — at the new Breakthrough Research Technologies session and the Silicon Innovation Forum at SEMICON West 2014. OSU metal cluster... » read more

Executive Insight: Aart de Geus
By Ed Sperling - 02 Jun, 2014 - Comments: 0

SE: What worries you most? De Geus: Everything I do is with high intensity, and what is of super high intensity right now—and there are challenges and opportunities in it—is that we have the confluence of some very big changes right now happening at the same time. On the technology side, there are multiple intersections. One is the intersection of another 10 years of Moore’s Law—finF... » read more

Tech Talk: Silicon Photonics
By Ed Sperling - 21 May, 2014 - Comments: 2

Mentor Graphics' John Ferguson explains why light is getting so much attention for inter-chip communications, where it excels, and why it has limitations. This is the first part in a two-part series. [youtube vid=0ydkDmrSrF4] » read more

Experts At The Table: What’s Next?
By Ed Sperling - 06 Jan, 2014 - Comments: 1

Semiconductor Engineering sat down with Sumit DasGupta, Si2; Simon Bloch, Samsung; Jim Hogan; Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: The future of technology isn’t just about technology. It’s about people and regulations, as well. Where are the hurdles ... » read more

System Bits: Dec. 10
By Brian Bailey - 10 Dec, 2013 - Comments: 0

Lasers From Nano Wires A few weeks ago, Semiconductor Engineering published a special report about silicon photonics and concentrated on the integration of the laser onto the silicon surface. Growing III-V materials on silicon is problematic because of the lattice mismatch, but researchers at the Technische Universität München (TUM) may have found a way around that problem. Thread-like semic... » read more

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