tag: SoC

Find The Best IP For You
By eSilicon - 26 Oct, 2016 - Comments: 0

It can be quite challenging and time consuming to find the right semiconductor IP for your project. You’ve got to find IP that does not consume too much power, meets your performance target, has the lowest leakage when your product goes on standby, and last but not least, IP that occupies the least amount of expensive real estate on your chip. How can you accomplish such a task without having... » read more

Executive Insight: Wally Rhines
By Ed Sperling - 06 Oct, 2016 - Comments: 0

[getperson id="11694" p_name="Wally Rhines"], chairman and CEO of [getentity id="22017" e_name="Mentor Graphics"], sat down with Semiconductor Engineering to talk about changes in automotive electronics, IoT security issues, and how this affects semiconductor design. What follows are excerpts of that conversation. SE: In automotive, one of the big changes is that we are no longer dealing wit... » read more

Back To Basics On Multi-Voltage Verification
By Srikanth Jadcherla - 11 Aug, 2016 - Comments: 0

It has been more than a decade since the paradigm of voltage-aware Booleans came about and the world of multi-voltage verification took off. We started with 3-5 island SoCs and now stare at 300+ islands on a single SoC. While we have a well-developed standard (IEEE 1801/UPF) for the expression and analysis of voltage variation, it is apt to not forget some of the basics and see how they will ca... » read more

Making Verification Easier
By Ann Mutschler - 28 Jul, 2016 - Comments: 0

SoC design teams increasingly are confronting complexity in the quest to target application segments, but at the same time they are struggling to more quickly reduce risk in their designs while also speed up testing to make sure everything works. Those often-conflicting goals have transformed [getkc id="10" kc_name="verification"] IP from an interesting concept to a must-have tool for advanc... » read more

How Cache Coherency Impacts Power, Performance
By Ann Mutschler - 27 Jul, 2016 - Comments: 0

As discussed in part one, one of the reasons cache coherency is becoming more important is the shared common memory resource in designs today. Various agents in the design want to access the data the fastest they can, putting pressure on the CPU complex to manage all of the requests. Until a generation ago, it was okay for the CPU to control that memory and have access to it, as well as be t... » read more

Architecting Memory For Next-Gen Data Centers
By Frank Ferro - 26 Jul, 2016 - Comments: 2

The industry’s insatiable appetite for increased bandwidth and ever-higher transfer rates is driven by a burgeoning Internet of Things (IoT), which has ushered in a new era of pervasive connectivity and generated a tsunami of data. In this context, datacenters are currently evaluating a wide range of new memory initiatives. All seek to optimize efficiency by reducing data transport, thus sign... » read more

How Cache Coherency Impacts Power, Performance
By Ann Mutschler - 18 Jul, 2016 - Comments: 2

Managing how the processors in an SoC talk to one another is no small feat, because these chips often contain multiple processing units and caches. Bringing order to these communications is critical for improving performance and [getkc id="106" kc_name="reducing power"]. But it also requires a detailed understanding of how data moves, the interaction between hardware and software, and what c... » read more

Executive Insight: Raik Brinkmann
By Ed Sperling - 06 Jul, 2016 - Comments: 0

[getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"], sat down with Semiconductor Engineering to discuss where and why formal verification is gaining traction, and how it fits alongside other verification approaches. What follows are excerpts of that conversation. SE: [getkc id="33" kc_name="Formal"] has been around for a whi... » read more

Can Verification Meet In The Middle?
By Brian Bailey - 30 Jun, 2016 - Comments: 0

Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

Executive Insight: Grant Pierce
By Ed Sperling - 29 Jun, 2016 - Comments: 0

Grant Pierce, president and CEO of Sonics, sat down with Semiconductor Engineering to discuss new ways to increase energy efficiency in SoCs. What follows are excerpts of that conversation. SE: Looking out at the semiconductor industry there are a lot of changes underway right now. What are the biggest impacts from your perspective? Pierce: The amount of data that is being captured or sen... » read more

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