Manufacturing Bits: May 26

By Mark LaPedus - 26 May, 2020 - Comments: 0

7-level nanosheets The 2020 Symposia on VLSI Technology & Circuits for the first time will be held as a virtual conference. The event, to be held from June 15-18, is organized around the theme “The Next 40 Years of VLSI for Ubiquitous Intelligence.” Among the papers at the event include advanced nanosheet transistors, 3D stacked memory devices and even an artificial iris. At the ... » read more

Making Chips At 3nm And Beyond

By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

EDA Gears Up For 3D

By Brian Bailey - 26 Aug, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor Business Unit of ANSYS; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Bus... » read more

Week In Review: Design, Low Power

By Jesse Allen - 26 Apr, 2019 - Comments: 0

A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog a... » read more

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tag: SoIC

Manufacturing Bits: May 26

Making Chips At 3nm And Beyond

EDA Gears Up For 3D

Week In Review: Design, Low Power

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