Chip Industry Week in Review

By The SE Staff - 30 May, 2025 - Comments: 1

The U.S. Commerce Department is tightening controls on EDA software sold to China by imposing additional license requirements. EDA companies are assessing the impact. Details on how broad the restrictions will be are still pending. The U.S. Federal Trade Commission (FTC) will require Synopsys and Ansys to divest key software assets — including optical, photonic, and RTL power analysis tool... » read more

Chip Industry Technical Paper Roundup: Apr. 22

By Linda Christensen - 22 Apr, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=421 /] Find more semiconductor research papers here. » read more

Single Transistor Memory Cell C2RAM Based On FDSOI For Quantum And Neuromorphic

By Technical Paper Link - 15 Apr, 2025 - Comments: 0

A new technical paper titled "An Energy Efficient Memory Cell for Quantum and Neuromorphic Computing at Low Temperatures" was published by researchers at Forschungszentrum Jülich, RWTH Aachen University and SOITEC. Abstract: "Efficient computing in cryogenic environments, including classical von Neumann, quantum, and neuromorphic systems, is poised to transform big data processing. The que... » read more

EU Chips Act: A Game Changer For The Digital Economy

By Maria Daniela Perez - 17 Dec, 2024 - Comments: 0

The global semiconductor landscape has undergone significant transformation in recent years. With disruptions such as the semiconductor supply chain crisis and the challenges it posed to the automotive sector, Europe’s dependence on external fabrication facilities, particularly in Taiwan, has become a pressing concern. In response, the European Union (EU) introduced the EU Chips Act, a compre... » read more

Chip Industry Week In Review

By The SE Staff - 15 Nov, 2024 - Comments: 0

CSIS issued a new report that says Intel is "not too big to fail, but too good to lose." The report noted that Intel is needed for national security, and that it must be viewed in a geopolitical context rather than from a purely business standpoint when it comes to funding the company. Japan's government is creating a 10 trillion yen (~$65 billion) fund for next-gen technologies, including A... » read more

Chip Industry Week In Review

By The SE Staff - 04 Oct, 2024 - Comments: 0

Amkor will provide turnkey advanced packaging and test services to TSMC in Amkor's planned facility in Peoria, Arizona, in a deal announced on Thursday. The companies jointly specified the packaging technologies, such as TSMC’s Integrated Fan-Out (InFO) and Chip on Wafer on Substrate (CoWoS). President Biden signed into law a bill that exempts some semiconductor projects funded by the U.S.... » read more

Chip Industry Week In Review

By The SE Staff - 13 Sep, 2024 - Comments: 0

Infineon rolled out the world's first 300mm gallium nitride (GaN) wafer, opening the door for high-volume manufacturing of GaN-based power semiconductors. A 300mm wafer contains 2.3 times as many chips per wafer as a 200mm wafer. Fig.1: Infineon's 300mm GaN wafer. Source: Infineon The Semiconductor Industry Association released its 2024 State of the U.S. Semiconductor Industry report th... » read more

Driving Cost Lower and Power Higher With GaN

By Anne Meixner - 06 Aug, 2024 - Comments: 0

Gallium nitride is starting to make broader inroads in the lower-end of the high-voltage, wide-bandgap power FET market, where silicon carbide has been the technology of choice. This shift is driven by lower costs and processes that are more compatible with bulk silicon. Efficiency, power density (size), and cost are the three major concerns in power electronics, and GaN can meet all three c... » read more

Chip Industry Week In Review

By The SE Staff - 12 Jul, 2024 - Comments: 0

The U.S. Department of Commerce issued a notice of intent  to fund new R&D activities to establish and accelerate domestic advanced packaging capacity. CHIPS for America expects to award up to $1.6 billion in funding innovation across five R&D areas, as outlined in the vision for the National Advanced Packaging Manufacturing Program (NAPMP), with about $150 million per award in each... » read more

Building CFETs With Monolithic And Sequential 3D

By Katherine Derbyshire - 22 Feb, 2024 - Comments: 0

Successive versions of vertical transistors are emerging as the likely successor to finFETs, combining lower leakage with significant area reduction. A stacked nanosheet transistor, introduced at N3, uses multiple channel layers to maintain the overall channel length and necessary drive current while continuing to reduce the standard cell footprint. The follow-on technology, the CFET, pushes... » read more

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