Executive Briefing: The End Of CMOS?


Steve Longoria, senior vice president of Soitec, talks with System-Level Design about why silicon on insulator has suddenly become essential to semiconductor manufacturing and what it will mean for Moore's Law. [youtube vid=kNl1RSEpqKc] » read more

CMP, ST et al offer 28nm FD-SOI for prototyping, research


Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ What would a port to 28nm FD-SOI do for your design?  A recent announcement by CMP, STMicroelectronics and Soitec invites you to find out.  Specifically, ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process – which uses innovative silicon substrates from Soitec and incorporates robust, compact model... » read more

SOI Conference Shows SOI Driving Key Roadmaps


By Adele Hars The 2011 IEEE SOI Conference, held in Tempe, AZ last week was not one to miss…but I did. Happily, I got the papers right away, along with observations shared by some of the folks who did get there. Highlights include excellent and insightful papers from ST, ARM, IBM, Intel, Leti, Peregrine and GlobalFoundries, plus many more that indicate SOI-based technologies are at th... » read more

Ultra-thin wafers for 450mm FD-SOI on schedule


While much of the focus on the impending move to 450mm has focused on the equipment challenges, the wafers themselves are of course the primordial consideration. Predictions are starting to mount up linking the move to 450mm with a move to fully-depleted silicon-on-insulator (FD-SOI). So the question needs to be asked: will the wafers be ready? Engineered substrates like SOI wafers need to ... » read more

FD-SOI Foundations Ready, Say Semi Execs


By Adele Hars SOI (especially fully depleted “FD-SOI”) was a hot topic in the video and audio interviews that Debra Vogler of SST released recently. Here are brief summaries of the most important SOI-related interviews – with top brass from Leti, Soitec, KT, EVG and Qcept –  that she made at Semicon West ’11. (If you need a quick backgrounder on FD-SOI basics, see this exp... » read more

Does SOI matter to the designers using the chips?


By Adele Hars Much of the SOI vs. bulk discussion zeros right in on the manufacturing bottom line:  which is cheaper?   And absolutely, customers want the most cost-effective solution.  But the best of all possible worlds is if you can save them money and give them all the bells and whistles they're looking for, too, right? [caption id="attachment_150" align="alignleft" width="150" capti... » read more

RF Substrate Technologies for Mobile Communications


Two Soitec Group managers -- Eric Desbonnets and Stéphane Laurent -- describe how SOI wafers support RF technology development. » read more

MEMS on SOI – Growing Fast and Faster


By Adele Hars In the latest ASN posting by Dr. Eric Mounier of Yole Developpement, “SOI for MEMS: A Promising Material”, he notes that SOI MEMS is growing at a CAGR (2011-2015) of 15.6%, compared to 8.1% for bulk silicon-based solutions. MEMS designers are doing amazing things on SOI – which would explain that impressive growth rate. [caption id="attachment_12" align="aligncenter... » read more

Design Impacts of Fully Depleted SOI


Xavier Cauchy, digital applications manager at Soitec, considers the design implications of fully depleted SOI technology, including models, low-power techniques for SoCs, and other issues at the 22nm node. “Compelling simulation and silicon data for nanometer scale transistors is becoming available. However, as potential users realize the many interests of this technology, the next question ... » read more

Frequently Asked Questions About FD-SOI


In a question and answer format, Xavier Cauchy, digital applications manager at Soitec ([email protected]) and François Andrieu, senior research engineer at LETI, raise some of the technical issues surrounding fully depleted SOI technology. The authors compare FD-SOI to FinFETs, describe how non-digital transistors can be handled, and provide a list of references for further reading. » read more

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