tag: Soitec

FD-SOI Workshop ppts – STM’s 1st 28nm FD-SOI product line
By Various Writers - 12 Mar, 2012 - Comments: 0

The SOI Consortium’s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights. STMicroelectronics In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product line b... » read more

Executive Briefing: The End Of CMOS?
By Ed Sperling - 14 Dec, 2011 - Comments: 0

Steve Longoria, senior vice president of Soitec, talks with System-Level Design about why silicon on insulator has suddenly become essential to semiconductor manufacturing and what it will mean for Moore's Law. [youtube vid=kNl1RSEpqKc] » read more

CMP, ST et al offer 28nm FD-SOI for prototyping, research
By Various Writers - 06 Nov, 2011 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ What would a port to 28nm FD-SOI do for your design?  A recent announcement by CMP, STMicroelectronics and Soitec invites you to find out.  Specifically, ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process – which uses innovative silicon substrates from Soitec and incorporates robust, compact model... » read more

SOI Conference Shows SOI Driving Key Roadmaps
By Various Writers - 21 Oct, 2011 - Comments: 0

By Adele Hars The 2011 IEEE SOI Conference, held in Tempe, AZ last week was not one to miss…but I did. Happily, I got the papers right away, along with observations shared by some of the folks who did get there. Highlights include excellent and insightful papers from ST, ARM, IBM, Intel, Leti, Peregrine and GlobalFoundries, plus many more that indicate SOI-based technologies are at th... » read more

Ultra-thin wafers for 450mm FD-SOI on schedule
By Various Writers - 03 Oct, 2011 - Comments: 0

While much of the focus on the impending move to 450mm has focused on the equipment challenges, the wafers themselves are of course the primordial consideration. Predictions are starting to mount up linking the move to 450mm with a move to fully-depleted silicon-on-insulator (FD-SOI). So the question needs to be asked: will the wafers be ready? Engineered substrates like SOI wafers need to ... » read more

FD-SOI Foundations Ready, Say Semi Execs
By Various Writers - 09 Sep, 2011 - Comments: 0

By Adele Hars SOI (especially fully depleted “FD-SOI”) was a hot topic in the video and audio interviews that Debra Vogler of SST released recently. Here are brief summaries of the most important SOI-related interviews – with top brass from Leti, Soitec, KT, EVG and Qcept –  that she made at Semicon West ’11. (If you need a quick backgrounder on FD-SOI basics, see this exp... » read more

Does SOI matter to the designers using the chips?
By Various Writers - 19 Aug, 2011 - Comments: 0

By Adele Hars Much of the SOI vs. bulk discussion zeros right in on the manufacturing bottom line:  which is cheaper?   And absolutely, customers want the most cost-effective solution.  But the best of all possible worlds is if you can save them money and give them all the bells and whistles they're looking for, too, right? [caption id="attachment_150" align="alignleft" width="150" capti... » read more

RF Substrate Technologies for Mobile Communications
By Various Writers - 23 May, 2011 - Comments: 0

Two Soitec Group managers -- Eric Desbonnets and Stéphane Laurent -- describe how SOI wafers support RF technology development. » read more

MEMS on SOI – Growing Fast and Faster
By Various Writers - 11 Apr, 2011 - Comments: 0

By Adele Hars In the latest ASN posting by Dr. Eric Mounier of Yole Developpement, “SOI for MEMS: A Promising Material”, he notes that SOI MEMS is growing at a CAGR (2011-2015) of 15.6%, compared to 8.1% for bulk silicon-based solutions. MEMS designers are doing amazing things on SOI – which would explain that impressive growth rate. [caption id="attachment_12" align="aligncenter... » read more

Design Impacts of Fully Depleted SOI
By Various Writers - 10 Feb, 2011 - Comments: 0

Xavier Cauchy, digital applications manager at Soitec, considers the design implications of fully depleted SOI technology, including models, low-power techniques for SoCs, and other issues at the 22nm node. “Compelling simulation and silicon data for nanometer scale transistors is becoming available. However, as potential users realize the many interests of this technology, the next question ... » read more

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