tag: Sondrel

Week In Review: Design, Low Power
By Jesse Allen - 17 May, 2019 - Comments: 0

Tools & IP Cadence introduced the Tensilica Vision Q7 DSP, which provides up to 1.82 TOPS and is specifically optimized for simultaneous localization and mapping (SLAM). The DSP has a very long instruction word (VLIW) SIMD architecture, an enhanced instruction set supporting 8/16/32-bit data types and optional VFPU support for single and half precision, and a number of iDMA enhancements in... » read more

The Week In Review: Design
By Jesse Allen - 04 May, 2018 - Comments: 0

M&A ANSYS finalized its acquisition of OPTIS. Founded in 1989, OPTIS provided software for scientific simulation of light, human vision and physics-based visualization. The acquisition boosts the company's automotive simulation portfolio with radar, lidar and camera simulation. Terms were not disclosed. IP Arm debuted the Cortex-M35P processor. Aimed at IoT applications, the IP combine... » read more

Blog Review: Mar. 14
By Jesse Allen - 14 Mar, 2018 - Comments: 0

Cadence's Meera Collier considers the issues of bias implementation in algorithms and AI systems, and whether immense training sets can really solve the problem. Mentor's Cristian Filip digs into the evolution of signal integrity analysis methods and why different data rates require different solutions. Synopsys' Naveen G explains key features introduced in the latest generation of interc... » read more

Custom Vs. Non-Custom Design
By Ed Sperling - 21 Dec, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss custom designs with Yong Pang, head of North American operations for [getentity id="22217" e_name="Imec"]; Phil Burr, director of portfolio product management for [getentity id="22186" e_name="Arm's"] embedded and automotive groups; Ambar Sarkar, chief technologist at eInfochips; and John Tinson, vice president of sales at Sondrel. What follows are ... » read more

Blog Review: Nov. 8
By Jesse Allen - 08 Nov, 2017 - Comments: 0

Synopsys' Eric Huang digs in to what's new with USB 3.2 and what's achieved by preserving the existing PHY signaling speeds. In a video, Mentor's Colin Walls provides tips on how to write debuggable and maintainable embedded code. Cadence's Paul McLellan listens in on a talk by Andrew Kahng of UC San Diego on the problem of scaling and why machine learning can improve EDA tools. Rambus... » read more

Blog Review: Oct. 25
By Jesse Allen - 25 Oct, 2017 - Comments: 0

Mentor's Joe Hupcey III explains the benefits of prioritizing faults with formal analysis before launching detailed fault verification. Cadence's Paul McLellan listens in as AMD's Mark Papermaster discusses what's needed to keep driving Moore's Law. Synopsys' Jesse Victors takes a look at ROCA, the latest flaw affecting RSA cryptography, and argues it may be time for a new encryption sche... » read more

How To Build An IoT Chip (Part 2)
By Ed Sperling - 18 Oct, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss IoT chip design issues with Jeff Miller, product marketing manager for electronic design systems in the Deep Submicron Division of [getentity id="22017" e_name="Mentor, a Siemens Business"]; Mike Eftimakis, IoT product manager in [getentity id="22186" e_name="Arm"]'s Systems and Software Group; and John Tinson, vice president of sales at Sondrel Ltd... » read more

Blog Review: Oct. 11
By Jesse Allen - 11 Oct, 2017 - Comments: 0

Mentor's Matthew Balance examines the separation of concerns between test intent and test realization in the Portable Stimulus specification. Synopsys' Deepak Nagaria checks out the features that makes LPDDR4 efficient in terms of power consumption, bandwidth utilization, data integrity and performance. Cadence's Meera Collier listens in as Chris Rowen considers whether AI processing shou... » read more

Blog Review: Sept. 20
By Jesse Allen - 20 Sep, 2017 - Comments: 0

Mentor's Jeff Miller warns that MEMS accelerometers are vulnerable to takeover using specially constructed sound waves, as demonstrated in a new paper. Synopsys' Pooja Gupta and Srinivas Vijayaragavan explain some major technology updates in SAS 24G with a look at Binary primitives, Extended Binary primitives and primitive parameters. Cadence's Paul McLellan shares highlights from TSMC's ... » read more

How To Build An IoT Chip
By Ed Sperling - 07 Sep, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss IoT chip design issues with Jeff Miller, product marketing manager for electronic design systems in the Deep Submicron Division of [getentity id="22017" e_name="Mentor, a Siemens Business"]; Mike Eftimakis, IoT product manager in [getentity id="22186" comment="ARM"]'s Systems and Software Group; and John Tinson, vice president of sales at Sondrel Lt... » read more

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