tag: Sonics

Semiconductor R&D Crisis Ahead?
By Ed Sperling - 26 Jun, 2014 - Comments: 0

Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and ... » read more

Without Moore’s Law: EDA
By Brian Bailey - 26 Jun, 2014 - Comments: 3

Semiconductor Engineering is examining the assertion about the end of Moore’s Law in a number of different ways. The special report, “Will 7nm and 5nm really happen?” looked at the technical aspects related to continuing into finer geometries. “Moore’s Law Tail No Longer Wagging the Dog” asked the question about the economics of people being able to afford to go to the latest node. ... » read more

It Takes An Army
By Ed Sperling - 05 Jun, 2014 - Comments: 0

Security has always been a two-way educational process. The bad guys figure out where the weaknesses are, and the good guys figure out how they got in and ways to prevent it. This worked fine for antivirus software in the early days of the PC era, because viruses typically were generalized and the damage they did was rather crude and frequently reversible. Increasingly, however, a deep under... » read more

Blog Review: June 4
By Ed Sperling - 04 Jun, 2014 - Comments: 0

Sonics' Drew Wingard looks at the challenges of IP integration, from standards to re-use to the need for intelligence on the network. Given the focus on IP integration, as well as the myriad challenges, this is very timely information. ARM's Karthik Ranjan has an interesting theory about why Java developers wear glasses. Ansys' Justin Nescott unearths the five most interesting engineering... » read more

Executive Insight: Grant Pierce
By Ed Sperling - 29 May, 2014 - Comments: 0

SE: What worries you most? Pierce: At the very top of my list is continuing to attract the talent into the company that we’ve managed to build up over time. Inside of Sonics, it’s a unique situation. We’re at the boundary between system-level architecture and chip-level micro-architecture for having what the system guys are looking for in the silicon. We need expertise in any IP that t... » read more

New Business Model: Flexible Silos
By Ed Sperling - 22 May, 2014 - Comments: 0

Operational silos within organizations have a long history of streamlining processes and maximize efficiency. In fact, that approach has made enterprise resource planning applications a must-have for most companies, and cemented the fortunes of giants such as SAP and Oracle, as well as the giant consulting companies that recommend them. But those kinds of delineations don’t work so well fo... » read more

When And Where To Use Virtual Prototypes
By Ann Mutschler - 22 May, 2014 - Comments: 0

Just because something is technically possible doesn’t always mean it should be done. This definitely holds true currently when it comes to virtual prototypes, which have gotten a lot of attention for their potential in the SoC design process—especially for concurrent software development. While no one is pointing fingers, there are situations in which design teams have thrown themselves... » read more

The Week In Review: Design
By Ed Sperling - 02 May, 2014 - Comments: 0

Tools CEVA integrated Bluetooth processing into its DSP cores. In addition to audio and video and always-on capabilities, the company is pitching the combination as an all-in-one, ultra-low-power solution for the wearable electronics market. So how big is this market opportunity? IDC predicts the wearable computing market will grow from 19.2 million units this year to 112 million units in 2... » read more

Efficiency Metrics Get Fuzzy
By Ed Sperling - 24 Apr, 2014 - Comments: 0

Not too long ago chipmakers used to measure transistors per hour and software developers would measure lines of code written per day or per week. Those metrics have fallen by the wayside—and chipmakers are still lamenting that loss. The problem is that nothing has come along to replace the old metrics, and complexity has left many chipmakers scratching their heads about how to build effici... » read more

Blog Review: April 16
By Ed Sperling - 16 Apr, 2014 - Comments: 0

Cadence’s Richard Goering attended a workshop on “extreme” scale design automation, which looked at where else EDA tools can be used—such as intelligent traffic lights. At least there are well-defined use cases. Mentor’s Nazita Saye has compiled five predictions from the 1964 New York World’s Fair that are worth revisiting. Three of them came true. Check out the ones that didn’... » read more

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