tag: Sonics

Pain Management
By Ed Sperling - 10 Apr, 2014 - Comments: 0

In part one of this series, the focus was on overlapping and new pain points in the semiconductor flow, from initial conception of what needs to be in a chip all the way through to manufacturing. Part two looks at how companies are attempting to manage that pain. It’s no secret that [getkc id="81" kc_name="SoC"]s are getting more complicated to design, debug and build, but the complexity i... » read more

New Approaches For Reliability
By Ed Sperling - 28 Mar, 2014 - Comments: 0

The definition of reliability hasn’t budged since the invention of the IC, but how to achieve it is starting to change. In safety-critical systems, as well as in markets such as aerospace, demands for reliability are so rigorous that they often require redundant circuitry—and for good reason. A PanAmSat malfunction in 1998 caused by tin whisker growth wiped out pagers for 45 million use... » read more

How Much Will That Chip Cost?
By Ed Sperling - 27 Mar, 2014 - Comments: 1

From the most advanced process nodes to the trailing edge of design there is talk about the skyrocketing cost of developing increasingly complex SoCs. At 16/14nm it’s a combination of multi-patterning, multiple power domains and factoring in physical and proximity effects. At older nodes, it’s the shift to more sophisticated versions of the processes and new tools to work within those proce... » read more

The Week In Review: Design
By Ed Sperling - 27 Mar, 2014 - Comments: 0

Tools Synopsys rolled out a major new release of its place and route tool, the centerpiece of its physical design platform, offering up to 10X improvement in speed—a combination of 5X faster implementation and 2X larger capacity. Co-CEO Aart de Geus called it the most significant product in the company’s history. Synopsys also rolled out an AMS verification platform to accelerate regres... » read more

The Week In Review: Design
By Ed Sperling - 21 Mar, 2014 - Comments: 0

Tools Mentor Graphics unveiled a new version of its PCB design platform, even going so far as to rename it slightly (Expedition to Xpedition). Mentor claims it’s the most significant product in that space in years, bridging the environments between designers and engineers. Included are placement planning in densely packed boards, which simplifies re-use and improves time to market, and elect... » read more

The Week In Review: Design
By Ed Sperling - 07 Mar, 2014 - Comments: 0

Tools Synopsys rolled out a new version of its software technologies for static and formal verification, which it says increases performance by up to five times. Also new are improved debug and low-power verification with native power simulation, and an integrated IP portfolio. Cadence uncorked a new version of its PCB and packaging environment, which it says speeds up timing closure by as ... » read more

The Week In Review: Design
By Ed Sperling - 28 Feb, 2014 - Comments: 0

Tools Cadence rolled out a new verification planning and management tool that is based on SQL, which greatly improves functionality and performance and offers multi-user, multi-engine and multi-analysis capabilities. Database technology—in this case, Structured Query Language—remains one of the very few software platforms that can harness multiple processors effectively. Synopsys unveil... » read more

10 Must Knows About Virtual Prototypes
By Brian Bailey - 27 Feb, 2014 - Comments: 1

1. What is a virtual prototype? If you ask a room full of people to define ‘system’, you will get as many answers as there are people in the room. The same is true for virtual prototypes. A virtual prototype defines a model of something that is usually created by one group and used by another with some implied abstraction. It is a prototype that exists as a software model on which analysis... » read more

Abstractions: The Good, Bad And Ugly
By Ed Sperling - 27 Feb, 2014 - Comments: 0

Raising the level of abstraction has become almost a mantra among chipmakers and tools developers. By moving the vantage point up a couple rungs on the ladder, it’s easier to see how the individual parts of a design go together, to identify problems in the design as well as fixes to problems, and it all can happen much more quickly. That’s the theory, at least. And in most cases, it’s ... » read more

Is Verification At A Crossroads?
By Ann Mutschler - 27 Feb, 2014 - Comments: 1

As SoC verification methodologies and technologies have continued to mature, it’s an interesting time for engineering teams as they look to meet time to market goals and cut costs in an environment of cutthroat profit margins. Whether it is hardware emulation, FPGA prototyping, virtual prototyping or traditional software simulation, each platform has its strengths and drawbacks, with overl... » read more

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