SRAM Cell Scaling With Monolithic 3D Integration Of 2D FETs (Penn State)


A new technical paper titled "Enabling static random-access memory cell scaling with monolithic 3D integration of 2D field-effect transistors" was published by researchers at The Pennsylvania State University. Abstract "Static Random-Access Memory (SRAM) cells are fundamental in computer architecture, serving crucial roles in cache memory, buffers, and registers due to their high-speed perf... » read more

CFETs: Reliability of Complementary Field-Effect Transistors (TU Munich, IIT)


A technical paper titled "CFET Beyond 3 nm: SRAM Reliability under Design-Time and Run-Time Variability" was published by researchers at TU Munich and IIT Kanpur. Abstract "This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging ef... » read more

Three-Way Race To 3D-ICs


Intel Foundry, TSMC, and Samsung Foundry are scrambling to deliver all the foundational components of full 3D-ICs, which collectively will deliver orders of magnitude improvements in performance with minimal power sometime within the next few years. Much attention has been focused on process node advances, but a successful 3D-IC implementation is much more complex and comprehensive than just... » read more

Impact Of Cryogenic Temps On The Minimum-Operating Voltage Of 5nm FinFETs-Based SRAM (IIT, UC Berkeley et al)


A new technical paper titled "An Investigation of Minimum Supply Voltage of 5nm SRAM from 300K down to 10K" was published by researchers at Indian Institute of Technology, UC Berkeley and Munich Institute of Robotics and Machine Intelligence. Abstract "In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum-operating voltage (Vmin) of 5 nm ... » read more

Photonic-SRAM Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems (UW, USC, GF)


A new technical paper titled "Design of Energy-Efficient Cross-coupled Differential Photonic-SRAM (pSRAM) Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems" was published by researchers at University of Wisconsin–Madison, USC and GlobalFoundries. Abstract "In this work, we propose a novel differential photonic static random access memory (pSRAM) bitcell design using fabri... » read more

Potential of AOS Memories As A High-Performance SRAM Substitute (Georgia Tech, U. of Virginia)


A new technical paper titled "Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache" was published by researchers at Georgia Institute of Technology and University of Virginia. Abstract: "The Last Level Cache (LLC) is the processor's critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low oper... » read more

Cracking The Memory Wall


Processor performance continues to improve exponentially, with more processor cores, parallel instructions, and specialized processing elements, but it is far outpacing improvements in bandwidth and memory. That gap, the so-called memory wall, has persisted throughout most of this century, but now it is becoming more pronounced. SRAM scaling is slowing at advanced nodes, which means SRAM takes ... » read more

Chiplets: Where Are We Today?


The 3rd annual Chiplet Summit was held in Santa Clara from January 21st to 23rd at the Convention Center. The conference continues to grow from its 1st year when it was held at the San Jose Doubletree Hotel (almost exactly 2 years ago). During his Chairman’s Welcome presentation, Chuck Sobey mentioned that there were 41 exhibitors at this year’s conference. Chuck was also the moderator f... » read more

SRAM With Mixed Signal Logic With Noise Immunity in 3nm Nanosheet (IBM)


A new technical paper titled "SRAM and Mixed-Signal Logic With Noise Immunity in 3nm Nano-Sheet Technology" was published by researchers at IBM T. J. Watson Research Center and IBM. Abstract "A modular 4.26Mb SRAM based on a 82Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3nm nanosheet (NS) technology. Designed macros ... » read more

Impact of Extremely Low Temperatures On The 5nm SRAM Array Size and Performance


A new technical paper titled "Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures" was published by researchers at University of Stuttgart, IIT Kanpur, National Yang Ming Chiao Tung University, Khalifa University, and TU Munich. Abstract "Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temp... » read more

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