Photonic-SRAM Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems (UW, USC, GF)


A new technical paper titled "Design of Energy-Efficient Cross-coupled Differential Photonic-SRAM (pSRAM) Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems" was published by researchers at University of Wisconsin–Madison, USC and GlobalFoundries. Abstract "In this work, we propose a novel differential photonic static random access memory (pSRAM) bitcell design using fabri... » read more

Potential of AOS Memories As A High-Performance SRAM Substitute (Georgia Tech, U. of Virginia)


A new technical paper titled "Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache" was published by researchers at Georgia Institute of Technology and University of Virginia. Abstract: "The Last Level Cache (LLC) is the processor's critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low oper... » read more

Cracking The Memory Wall


Processor performance continues to improve exponentially, with more processor cores, parallel instructions, and specialized processing elements, but it is far outpacing improvements in bandwidth and memory. That gap, the so-called memory wall, has persisted throughout most of this century, but now it is becoming more pronounced. SRAM scaling is slowing at advanced nodes, which means SRAM takes ... » read more

Chiplets: Where Are We Today?


The 3rd annual Chiplet Summit was held in Santa Clara from January 21st to 23rd at the Convention Center. The conference continues to grow from its 1st year when it was held at the San Jose Doubletree Hotel (almost exactly 2 years ago). During his Chairman’s Welcome presentation, Chuck Sobey mentioned that there were 41 exhibitors at this year’s conference. Chuck was also the moderator f... » read more

SRAM With Mixed Signal Logic With Noise Immunity in 3nm Nanosheet (IBM)


A new technical paper titled "SRAM and Mixed-Signal Logic With Noise Immunity in 3nm Nano-Sheet Technology" was published by researchers at IBM T. J. Watson Research Center and IBM. Abstract "A modular 4.26Mb SRAM based on a 82Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3nm nanosheet (NS) technology. Designed macros ... » read more

Impact of Extremely Low Temperatures On The 5nm SRAM Array Size and Performance


A new technical paper titled "Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures" was published by researchers at University of Stuttgart, IIT Kanpur, National Yang Ming Chiao Tung University, Khalifa University, and TU Munich. Abstract "Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temp... » read more

Design-Space Analysis of M3D FPGA With BEOL Configuration Memories (Georgia Tech, UCLA)


A new technical paper titled "Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories" was published by researchers at Georgia Tech and UCLA. Abstract "This work presents a novel monolithic 3D (M3D) FPGA architecture that leverages stackable back-end-of-line (BEOL) transistors to implement configuration memory and pass gates, significantly improving area, latency, and power ef... » read more

SRAM PUF – The Secure Silicon Fingerprint


For many years, silicon Physical Unclonable Functions (PUFs) have been seen as a promising and innovative security technology making steady progress. Today, Static Random-Access Memory (SRAM)-based PUFs have been deployed in hundreds of millions of devices and offer a mature and viable security component that is achieving widespread adoption in commercial products. They are found in devices ran... » read more

Fine-Grained Functional Partitioning For Low Level SRAM Cache in 3D-IC designs (imec)


A new technical paper titled "Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs" was published by researchers at imec. "We propose a partitioning of low-level (faster access) caches in 3D using an Array Under CMOS (AuC) technology paradigm. Our study focuses on partitioning and optimization of SRAM bit-cells and peripheral circuits, enabling heterogeneous ... » read more

Memory Fundamentals For Engineers


Memory is one of a very few elite electronic components essential to any electronic system. Modern electronics perform extraordinarily complex duties that would be impossible without memory. Your computer obviously contains memory, but so does your car, your smartphone, your doorbell camera, your entertainment system, and any other gadget benefiting from digital electronics. This eBook prov... » read more

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