tag: SRAM

HBM Issues In AI Systems
By Brian Bailey - 16 Mar, 2020 - Comments: 0

All systems face limitations, and as one limitation is removed, another is revealed that had remained hidden. It is highly likely that this game of Whac-A-Mole will play out in AI systems that employ high-bandwidth memory (HBM). Most systems are limited by memory bandwidth. Compute systems in general have maintained an increase in memory interface performance that barely matches the gains in... » read more

An Increasingly Complicated Relationship With Memory
By Brian Bailey - 27 Feb, 2020 - Comments: 4

The relationship between a processor and its memory used to be quite simple, but in modern SoCs there are multiple heterogeneous processors and accelerators, each needing a different means of accessing memory for maximum efficiency. Compromises are being made in order to preserve the unified programming model of the past, but the pressures are increasing for some fundamental changes. It does... » read more

Software In Inference Accelerators
By Ed Sperling - 10 Feb, 2020 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about the importance of hardware-software co-design for inference accelerators, how that affects performance and power, and what new approaches chipmakers are taking to bring AI chips to market. » read more

Balancing Flexibility And Quality In SRAM Verification
By Elven Huang - 30 Jan, 2020 - Comments: 0

Memory is an essential component of system-on-chip (SOC) designs, especially at advanced nodes. SoCs use a variety of memory block types, such as static random-access memory (SRAM) and dynamic RAM (DRAM), to perform computations. The SRAM blocks, which consist of an assembly of specialized calls that abut or overlap one another in a specific arrangement that complies with the circuit specificat... » read more

DRAM Scaling Challenges Grow
By Mark LaPedus - 21 Nov, 2019 - Comments: 5

DRAM makers are pushing into the next phase of scaling, but they are facing several challenges as the memory technology approaches its physical limit. DRAM is used for main memory in systems, and today’s most advanced devices are based on roughly 18nm to 15nm processes. The physical limit for DRAM is somewhere around 10nm. There are efforts in R&D to extend the technology, and ultimate... » read more

GDDR6 Drilldown: Applications, Tradeoffs And Specs
By Ed Sperling - 15 Nov, 2019 - Comments: 0

Frank Ferro, senior director of product marketing for IP cores at Rambus, drills down on tradeoffs in choosing different DRAM versions, where GDDR6 fits into designs versus other types of DRAM, and how different memories are used in different vertical markets. » read more

Pushing Memory Harder
By Brian Bailey - 14 Oct, 2019 - Comments: 4

In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

Memory Subsystems In Edge Inferencing Chips
By Ed Sperling - 23 Sep, 2019 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about key issues in a memory subsystem in an inferencing chip, how factors like heat can affect performance, and where these kinds of chips will be used. » read more

Why DRAM Won’t Go Away
By Ed Sperling - 18 Sep, 2019 - Comments: 0

Semiconductor Engineering sat down to talk about DRAM's future with Frank Ferro, senior director of product management at Rambus; Marc Greenberg, group director for product marketing at Cadence; Graham Allan, senior product marketing manager for DDR PHYs at Synopsys; and Tien Shiah, senior manager for memory marketing at Samsung Electronics. What follows are excerpts of that conversation. Part ... » read more

Machine Learning Inferencing At The Edge
By Ed Sperling - 12 Sep, 2019 - Comments: 1

Ian Bratt, fellow in Arm's machine learning group, talks about why machine learning inferencing at the edge is so difficult, what are the tradeoffs, how to optimize data movement, how to accelerate that movement, and how it differs from developing other types of processors. » read more

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