tag: stacked die

Deep Inside Intel
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Mark Bohr, senior fellow at Intel, to talk about a wide range of manufacturing and design issues Intel is wrestling with at advanced nodes—and just how far the road map now extends. SMD: Will EUV make 10nm? And if it doesn’t, what effect will that have on Intel? Bohr: For a process module as critical as lithography... » read more

New Math
By Ed Sperling - 18 Oct, 2012 - Comments: 0

It was nice when we had round numbers to work with. It was pretty simple to move from 180nm to 120nm and then to 90nm. Then the half nodes started—45/40, 32/28 and 22/20nm. After 14nm we are poised dangerously over the single-digit process nodes. Intel is working on 10nm, to be followed by 7nm or 5nm. Other companies are looking at 11nm, to be followed by 8nm, 6nm or something even further... » read more

Thanks For The Memories
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The amount of real estate in a design now devoted to memories—SRAM on chip, DRAM off chip, and a few other more exotic options showing up occasionally—is a testament to the amount of data that needs to be utilized quickly in both mobile and fixed devices. Memory is almost singlehandedly responsible for the routing congestion now plaguing complex SoCs. It is one of the mai... » read more

Materials, Architectures And Gordon Moore
By Ed Sperling - 21 Sep, 2012 - Comments: 0

Shrinking features on bulk CMOS using planar transistors has turned the semiconductor industry from a startup industry to one of the most efficient and robust industries in the world. Each new process node increases the number of chips that can be cut out of a single wafer, literally defining economies of scale. Gordon Moore defined the direction, which certainly created a long list of chall... » read more

Experts At The Table: IC Manufacturing Challenges
By Ed Sperling - 20 Sep, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future manufacturing challenges with Carlos Mazure, chief technical officer at Soitec; Jeff Hebb, vice president of laser product marketing at Ultratech; Markus Wimplinger, corporate technology development and IP director at EV Group; and Girish Dixit, vice president of the customer integration center and process inte... » read more

Testing One, Two, Three
By Ed Sperling - 20 Sep, 2012 - Comments: 0

The sheer number of off-the-shelf parts that are showing up in ICs these days—and that includes both hard and soft parts—means that to a large extent we are designing and manufacturing a series of interconnected black boxes. Black boxes, at least in theory, are a major time saver. The idea that you can put together a series of well-designed, state-of-the-art Lego-like blocks that are pro... » read more

Experts At The Table: Stacked Die Reality Check
By Ed Sperling - 27 Aug, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries; Steve Pateras, product marketing director at Mentor Graphics; Steve Smith, senior director of platform marketing at Synopsys; Thorsten Matthias, business development director at EVGroup; and Manish Ranjan, vice president of market... » read more

Inflection Points Ahead
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Engineering challenges have existed at every process node in semiconductor designs, but at 20nm and beyond, engineers and executives on all sides of the industry are talking about inflection points. An inflection point is literally the place where a curve on a graph turns down or up, but in the semiconductor industry it’s usually associated with the point at which a progres... » read more

Dealing With Test More Effectively
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Shrinking geometries are starting to have the same effect on test as they are on other parts of an SoC, with the focus shifting from area to leakage, heat, noise, signal integrity, and the impact on overall system performance. The warning that design teams have to consider test much earlier in the design was issued to chipmakers years ago and largely ignored. At 28nm that war... » read more

Experts at the Table: Stacking the Deck
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss challenges to 3D-IC adoption with Samta Bansal, product marketing for applied silicon realization in strategy and market development at Cadence; Carey Robertson, product marketing director at Mentor Graphics; Karthik Chandrasekar, member of technical staff in IC Design at Altera; and Herb Reiter, president of EDA2ASIC Consulting... » read more

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