tag: stacked die

Materials, Architectures And Gordon Moore
By Ed Sperling - 21 Sep, 2012 - Comments: 0

Shrinking features on bulk CMOS using planar transistors has turned the semiconductor industry from a startup industry to one of the most efficient and robust industries in the world. Each new process node increases the number of chips that can be cut out of a single wafer, literally defining economies of scale. Gordon Moore defined the direction, which certainly created a long list of chall... » read more

Experts At The Table: IC Manufacturing Challenges
By Ed Sperling - 20 Sep, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future manufacturing challenges with Carlos Mazure, chief technical officer at Soitec; Jeff Hebb, vice president of laser product marketing at Ultratech; Markus Wimplinger, corporate technology development and IP director at EV Group; and Girish Dixit, vice president of the customer integration center and process inte... » read more

Testing One, Two, Three
By Ed Sperling - 20 Sep, 2012 - Comments: 0

The sheer number of off-the-shelf parts that are showing up in ICs these days—and that includes both hard and soft parts—means that to a large extent we are designing and manufacturing a series of interconnected black boxes. Black boxes, at least in theory, are a major time saver. The idea that you can put together a series of well-designed, state-of-the-art Lego-like blocks that are pro... » read more

Experts At The Table: Stacked Die Reality Check
By Ed Sperling - 27 Aug, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries; Steve Pateras, product marketing director at Mentor Graphics; Steve Smith, senior director of platform marketing at Synopsys; Thorsten Matthias, business development director at EVGroup; and Manish Ranjan, vice president of market... » read more

Inflection Points Ahead
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Engineering challenges have existed at every process node in semiconductor designs, but at 20nm and beyond, engineers and executives on all sides of the industry are talking about inflection points. An inflection point is literally the place where a curve on a graph turns down or up, but in the semiconductor industry it’s usually associated with the point at which a progres... » read more

Dealing With Test More Effectively
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Shrinking geometries are starting to have the same effect on test as they are on other parts of an SoC, with the focus shifting from area to leakage, heat, noise, signal integrity, and the impact on overall system performance. The warning that design teams have to consider test much earlier in the design was issued to chipmakers years ago and largely ignored. At 28nm that war... » read more

Experts at the Table: Stacking the Deck
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss challenges to 3D-IC adoption with Samta Bansal, product marketing for applied silicon realization in strategy and market development at Cadence; Carey Robertson, product marketing director at Mentor Graphics; Karthik Chandrasekar, member of technical staff in IC Design at Altera; and Herb Reiter, president of EDA2ASIC Consulting... » read more

Preparing For Change
By Ed Sperling - 16 Aug, 2012 - Comments: 0

Throw out the most optimistic and the most pessimistic predictions about the future of the foundry model and you probably arrive at a reasonable approximation of how things will actually play out. It's clear that the number of customers at the front end of process technology will shrink after 20nm. It simply costs too much to design and manufacture a chip, and there aren’t enough markets c... » read more

Litho Community Meets And Votes
By Marc David Levenson - 31 Jul, 2012 - Comments: 0

Every 18 months or so, the leading lithography lights of the IEEE meet in an off-the-record workshop to discuss the state and future of our craft. This year’s event took place amid the restored colonial splendor of Williamsburg Virginia in June. Co-chairs Mordechai Rothschild and Lars Liebmann assembled a technical program that covered not only lithography for semiconductor manufacturing, but... » read more

Firms Rethink Fabless-Foundry Model
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Mark LaPedus As chipmakers move toward 20nm designs, finFETs and 3D stacked devices, the industry is beginning to re-think the fabless-foundry model. Leading-edge foundries are finally getting serious about the “virtual IDM” model, in which vendors will act more like integrated device manufacturers (IDMs), as opposed to being mere production partners. In this model, the found... » read more

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