tag: stacked die

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: If you ar... » read more

No Road, No Roadmap
By Atrenta - 06 Dec, 2012 - Comments: 0

Happy holidays! It’s almost that time of year. Well-wishing and celebration are customary around now. I’ll get to that in a moment. But so are retrospectives and prognostication. Let’s focus on those for a moment. What has 2012 brought us, and what lies ahead? While there have been many technology advances and exciting new product introductions this past year, one fact shines through a... » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: If you ar... » read more

MEMS Goes Mainstream
By Ed Sperling - 29 Nov, 2012 - Comments: 0

By Cheryl Coupé Micro-electromechanical systems (MEMS) are well known for enabling innovative capabilities for devices that range from vehicles and gaming to smartphones and tablets—and increasingly in personal health and fitness, security, and environmental applications. As stacked die become more popular, they also will become part of the integration challenge that chipmakers will wrestle... » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 16 Nov, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: What effe... » read more

New Apps For 3D Chips
By Ed Sperling - 15 Nov, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing and; Design sat down to discuss the 3D device challenges and applications with Peter Ramm, head of the department for device and 3D integration at Fraunhofer EMFT Munich, one of Europe’s largest research organizations. SMD: Fraunhofer was a pioneer in 3D chip R&D, right? Ramm: We are the oldest microelectronics institute in Germany. We st... » read more

Experts At The Table: The Sky Isn’t Falling
By Ann Mutschler - 15 Nov, 2012 - Comments: 0

By Ann Steffora Mutschler Semiconductor Manufacturing and Design sat down recently to discuss how the industry is making 3D ICs a reality today with Sylvan Kaiser, chief technology officer at Docea Power; Steve Smith, senior director for 3D-IC strategy at Synopsys; and Ahmed Jerraya, director of strategic design programs at CEA-LETI. SMD: How far are we from having the models we need to ena... » read more

Deep Inside Intel
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Mark Bohr, senior fellow at Intel, to talk about a wide range of manufacturing and design issues Intel is wrestling with at advanced nodes—and just how far the road map now extends. SMD: Will EUV make 10nm? And if it doesn’t, what effect will that have on Intel? Bohr: For a process module as critical as lithography... » read more

New Math
By Ed Sperling - 18 Oct, 2012 - Comments: 0

It was nice when we had round numbers to work with. It was pretty simple to move from 180nm to 120nm and then to 90nm. Then the half nodes started—45/40, 32/28 and 22/20nm. After 14nm we are poised dangerously over the single-digit process nodes. Intel is working on 10nm, to be followed by 7nm or 5nm. Other companies are looking at 11nm, to be followed by 8nm, 6nm or something even further... » read more

Thanks For The Memories
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The amount of real estate in a design now devoted to memories—SRAM on chip, DRAM off chip, and a few other more exotic options showing up occasionally—is a testament to the amount of data that needs to be utilized quickly in both mobile and fixed devices. Memory is almost singlehandedly responsible for the routing congestion now plaguing complex SoCs. It is one of the mai... » read more

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