tag: stacked die

Experts At The Table: Stacking The Deck
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler There is no doubt 3D stacking brings challenges not only from the design perspective, but also on the tool side. EDA vendors have been working for more than a few years to ready tools for stacked-die designs. How smooth the transition is, however, is a big question mark. Because the approach is new, not all the challenges are fully understood yet. And while most ED... » read more

Routing Congestion Returns
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Routing congestion has returned with a vengeance to SoC design, fueled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors. This is certainly not a foreign concept for IC design. The markets for place and route tools were driven largely by the need to automate this kind of operat... » read more

SoC Platforms Gain Steam
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Platforms are attracting far more attention from makers of SoCs because they are pre-verified and can speed time to market, but the shift isn’t so simple. It will spark major changes in the way companies design and build chips, causing significant disruption across the entire SoC ecosystem. Platforms are nothing new in the processor and software world. Intel, IBM AMD, and N... » read more

Achieving Fast And Accurate Extraction Of 3D-IC Layout Structures
By Various Writers - 26 Jul, 2012 - Comments: 0

The electronics industry is devoting a lot of energy to exploring “More than Moore’s Law” approaches that drive continued value scaling through system integration, rather than (or in addition to) shrinking transistors. One of the most promising techniques is the creation of 3D-ICs using TSV structures. However, accurately modeling a 3D multi-die system requires tools that extract precise ... » read more

Experts At The Table: Pain Points
By Ed Sperling - 20 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: With stacked die it’s no longer one company making an SoC. W... » read more

Future Foundry Issues
By Ed Sperling - 13 Jul, 2012 - Comments: 0

Semiconductor Manufacturing & Design talks with Luigi Capodieci, fellow at GlobalFoundries, about EUV, the challenges at 20nm and beyond, and the future of the foundry model. [youtube vid=YXov4y0kpfU] » read more

Disaggregation And Re-aggregation
By Ed Sperling - 02 Jul, 2012 - Comments: 0

The proliferation of platforms, subsystems and IP of any sort, as well as the move to stack die in 2.5D configurations, will force a realignment of the ecosystem. For the moment, it appears that vertically integrated companies such as Apple and Samsung have a distinct advantage. It remains to be seen just how substantial that advantage really is, however. As chips become a collection of more... » read more

Challenges Mount For Interconnect
By Mark LaPedus - 26 Jun, 2012 - Comments: 0

By Mark LaPedus There are a plethora of chip-manufacturing challenges for the 20nm node and beyond. When asked what are the top challenges facing leading-edge chip makers today, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, said it boils down to two major hurdles: lithography and the interconnect. The problems with lithography are well documented.... » read more

Bucket Lists
By Ed Sperling - 26 Jun, 2012 - Comments: 0

At 130nm, the introduction of copper interconnects, 300mm wafers and low-k dielectrics left the entire supply chain breathless. There had never been as many changes at a single process node in the history of semiconductors. At 28nm, the number of changes will pale compared to what’s necessary at 20nm, and that will pale to what’s required at 14nm. But unlike 130nm, when most of those cha... » read more

Power Shift
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ed Sperling For the past decade, most of the real gains in energy efficiency were developed for chips inside mobile electronics because of the demand for longer battery life. Dark silicon now represents the majority of mobile devices, multiple power islands are commonplace to push many functions into deep sleep, and performance is usually the secondary concern for most applications. Whil... » read more

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