tag: stacked die

Packaging Tradeoffs More Complex Than Ever
By Ed Sperling - 24 May, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by high-speed interfaces, the demand for TSVs and the complexities that new process nodes bring, older packaging technologies like wirebonding can’t keep up. The latest and greatest flip chip technologies offer much more flexibility, but at a cost. As such, the package plays a larger role than ever in determining system specifications because, depending o... » read more

Managing Complexity With Advanced Packaging
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ann Steffora Mutschler Engineering teams across the globe continue to pound the process geometry treadmill to stay on the curve of Dr. Moore to achieve better speed or lower power or smaller die—and it all adds up to increased complexity in the design and packaging. However, with advanced forms of die stacking such as package-on-package, silicon-in-package, 2.5D silicon interposer techno... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 09 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wh... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 02 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wh... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 22 Feb, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wha... » read more

Off The Planar
By Ed Sperling - 15 Dec, 2011 - Comments: 0

By Pallab Chatterjee 3D devices, FinFETs and new memory technologies are not just a future direction anymore. They’re real. That became evident at this year’s IEDM conference, where the focus of a number of sessions was on modeling, failure and reliability models, as well as lower power supply operations for these devices. Because FinFETs are not standard 2D MOS devices, their use i... » read more

Something Old, Something Borrowed
By Ed Sperling - 11 Nov, 2011 - Comments: 0

The basic rule of SoC design is that it needs to be created relatively quickly, work as planned, and that it can be manufactured at a reasonable cost and with good yield ramp. That eliminates revolutionary changes on the technology side, limits the number of new materials, and relegates the most dramatic shifts to the business. That’s why most of the most far-reaching technology research i... » read more

Performance Plus Lower Power
By Ed Sperling - 06 Oct, 2011 - Comments: 0

A new race is beginning in the SoC world. While performance has been supplanted by battery life as the top goal for the next process node, that prioritization isn’t going to last. The ultimate challenge will be to achieve both—higher performance with substantially lower power. This is the subject of research inside of dozens of companies and universities, and there are several different... » read more

Will Wide I/O Reduce Cache?
By Ed Sperling - 25 Aug, 2011 - Comments: 0

By Ann Steffora Mutschler In an ideal world, all new SoC technologies would make the lives of design engineers easier. While this may be true of some techniques, it is not the case with one advanced memory interface technology on the horizon, Wide I/O. There are claims that Wide I/O could reduce cache, but so far this is not widely understood. In fact, exactly how Wide I/O will be used, wha... » read more

Solving Memory Subsystem Bottlenecks In 3D Stacks
By Ann Mutschler - 28 Jul, 2011 - Comments: 0

In today’s do-or-die market environment, many SOC makers strive to differentiate their product based upon the rate at which it performs processing. Closely coupled are power concerns that have led to dominance of a multi-core approach, while economic considerations have resulted in the dominance of the Unified Memory Architecture, where all the processors share access to external DRAM. Stacki... » read more

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