Off The Planar

By Pallab Chatterjee
3D devices, FinFETs and new memory technologies are not just a future direction anymore. They’re real.

That became evident at this year’s IEDM conference, where the focus of a number of sessions was on modeling, failure and reliability models, as well as lower power supply operations for these devices.

Because FinFETs are not standard 2D MOS devices, their use in circuit applications is also different. A number of papers have been submitted about multi-gate device structures for these 3D devices and the associated variability and sensitivity effects. These devices do resolve some of the design issues that arise from traditional 2D device scaling, but they also introduce new challenges.

Channel and source/drain doping profiles and conformity, gate underlap and final profiles of the well and halo implants have a large impact on the performance of the resulting devices. These issues currently are being investigated in the context of production-scale metrology to verify the device performance in manufacturing and to ensure the device models are met. Additionally, the tradeoff for Vt variation minimization by the high electrostatic integrity—as well as tolerance to low channel doping benefits of the FinFET—is offset by the further variability to line edge roughness (both gate edge roughness and fin edge roughness), metal gate granularity and interface trapped charges. These effects are in addition to the random discrete dopant variation.

Other devices such as those based on ETSOI (extremely thin silicon on insulator) have systematic variability issues related to the Vt of the devices rather than just implant sensitivity. This has a significant impact on device orientation and grouping for matched signal paths. For both planar and vertical fin-like structures, IBM and Leti have developed expectations of the influence of silicon thickness on transistor threshold voltage matching. The thickness data suggest a strong dependence of matching on transistor spacing and a weak dependence on transistor area. This is contrary to larger-geometry devices, where the dependence is primarily on transistor area.

Continuing on the SOI devices, a design method to minimize drain current mismatch was presented at the conference. The technique, called the Self-Heating induced Feedback Effect (SHFE) is designed for ultra-thin-body and multi-gate transistors on SOI or ETSOI. The performance results, and the probability of impact of the effect for this technique, varied based on the orientation of the material used for the SOI device. It ranged from 60% for material down to 40% for material.

These effects are best modeled on statistically distributed electrical parameters that evolve with time basis. The time-dependent device variability is realized as a shifting of the values of the circuit parameters, which can lead to reduction in circuit yield and/or reliability of the design. The effects for these nanoscale devices and their modeling includes several main aging mechanisms, such as Bias Temperature Instabilities (BTI), channel hot carrier (CHC) degradation and dielectric breakdown. To address these effects the designer must return to an older design methodology where there was a strong link between the circuit design and the fundamental device technology. After this link is established and validated at the primitive levels of the design, devices and multi-gate device groups then create new levels of functional abstraction.

Designers have a number of new issues to review for these new technologies. The devices are no longer planar and there are new elements and materials in use. At the conference, the following elements were now introduced to the semiconductor flow in addition to the traditional Si, Al, Cu, As, P and B. The new elements in the mainstream of the design include Pr, Mn, Ca, Ti, In, Ga, Zn, Hg, I, W, Sn, Zr, Cd, Ge, N, Te and mixed III-V compounds, either as mixed die or thin film on Si. This shift brings the material science aspects of understanding variability and secondary effects (temperature coefficient, voltage coefficient, EM, ESD, etc.) to the forefront of the device design activity.