tag: Stanford University

Blog Review: March 4
By Jesse Allen - 04 Mar, 2020 - Comments: 0

Mentor's Shivani Joshi provides a primer on design rule checks and how they can help flag potential issues in PCB design. Synopsys' Taylor Armerding argues that while better IoT security requires a change in consumer culture and habits, manufacturers and government should be doing more as well. Cadence's Johnas Street chats with several colleagues about what Black History Month means to t... » read more

Power/Performance Bits: Feb. 18
By Jesse Allen - 18 Feb, 2020 - Comments: 0

Cryogenic memory Researchers at Oak Ridge National Laboratory demonstrated a new cryogenic memory cell circuit design based on coupled arrays of Josephson junctions. Such a memory could help enable exascale and quantum computing. The cells are designed to operate in super cold temperatures and were tested at just 4 Kelvin above absolute zero, about minus 452 degrees Fahrenheit. At these col... » read more

Power/Performance Bits: Jan. 28
By Jesse Allen - 28 Jan, 2020 - Comments: 0

Accelerator-on-chip Researchers at Stanford University and SLAC National Accelerator Laboratory created an electron-accelerator-on-chip. While the technique is much less powerful than standard particle accelerators, it can be much smaller. It relied upon an infrared laser to deliver, in less than a hair’s width, the sort of energy boost that takes microwaves many feet. The team carved ... » read more

Plasticine: A Reconfigurable Architecture For Parallel Patterns (Stanford)
By Technical Paper Link - 16 Jan, 2020 - Comments: 0

Source: Stanford University Stanford University has been developing Plasticine, which allows parallel patterns to be reconfigured. "ABSTRACT Reconfigurable architectures have gained popularity in recent years as they allow the design of energy-efficient accelerators. Fine-grain fabrics (e.g. FPGAs) have traditionally suffered from performance and power inefficiencies due to bit-level ... » read more

More Knobs, Fewer Markers
By Ed Sperling - 16 Jan, 2020 - Comments: 0

The next big thing in chip design may be really big — the price tag. In the past, when things got smaller, so did the cost per transistor. Now they are getting more expensive to design and manufacture, and the cost per transistor is going up along with the number of transistors per area of die, and in many cases even the size of the die. That's not exactly a winning economic formula, which... » read more

Priorities Shift In IC Design
By Ann Mutschler - 16 Jan, 2020 - Comments: 0

The rush to the edge and new applications around AI are causing a shift in design strategies toward the highest performance per watt, rather than the highest performance or lowest power. This may sound like hair-splitting, but it has set a scramble in motion around how to process more data more quickly without just relying on faster processors and accelerators. Several factors are driving th... » read more

Power Complexity On The Rise
By Ann Mutschler - 14 Nov, 2019 - Comments: 0

New chip architectures and custom applications are adding significant challenges to chip design and verification, and the problems are becoming much more complex as low power is added into the mix. Power always has been a consideration in design, but in the past it typically involved different power domains that were either on, off, or in some level of sleep mode. As hardware architectures s... » read more

Revving Up For Edge Computing
By Ed Sperling - 07 Nov, 2019 - Comments: 1

The edge is beginning to take shape as a way of limiting the amount of data that needs to be pushed up to the cloud for processing, setting the stage for a massive shift in compute architectures and a race among chipmakers for a stake in a new and highly lucrative market. So far, it's not clear which architectures will win, or how and where data will be partitioned between what needs to be p... » read more

Power/Performance Bits: Oct. 1
By Jesse Allen - 01 Oct, 2019 - Comments: 0

Nighttime power Researchers at UCLA and Stanford University created a low-cost device that harnesses radiative cooling to provide a small amount of renewable energy at night. While the device only provides a small amount of power, it could be useful for areas without reliable electricity or access to batteries. Radiative cooling happens when a surface that faces the sky emits heat as therma... » read more

Week in Review – IoT, Security, Autos
By Jeff Dorsch - 27 Sep, 2019 - Comments: 0

Products/Services Achronix Semiconductor joined Taiwan Semiconductor Manufacturing’s IP Alliance Program, part of the foundry’s Open Innovation Platform. Achronix’s Speedcore eFPGA IP is available today on TSMC 16nm FinFET Plus (16FF+) and N7 process technologies, and it will be soon available on TSMC 12nm FinFET Compact Technology (12FFC). Cadence Design Systems announced that its di... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy