MEMS Foundries Play Waiting Game


By Mark LaPedus For years, the foundries in the microelectromechanical systems (MEMS) business have been patiently waiting for the MEMS integrated device manufacturers (IDMs) to outsource some or all of their production. The MEMS foundries are still waiting for that development. Because MEMS are custom devices tuned to a proprietary process and toolset, IDMs still prefer to use their own f... » read more

Trading Off Power And Performance


By Ann Steffora Mutschler There is no shortage of opinions when it comes to the topic of performance and power tradeoffs. From abstracting the task from engineers to process considerations, engineering teams have a number of tools and approaches at their disposal to make the optimal design choices for their application. Take the MCU application space for instance. Ken Dwyer, director of app... » read more

Dealing With New Bottlenecks


By Ed Sperling While the number of options for improving efficiency and performance in designs continues to increase, the number of challenges in getting chips at advanced process nodes out the door is increasing, too. Thinner wires, routing congestion, more power domains, IP integration and lithography issues are conspiring to make design much more difficult than in the past. So why aren�... » read more

To DVFS Or Not To DVFS


I’m in a great position to hear lots of interesting opinions about technology today and this week was no different. During a discussion with Atrenta CTO Bernard Murphy about power and performance tradeoffs, he mentioned that he is not hearing a lot of engineering teams using DVFS (dynamic voltage and frequency scaling) because it creates complications for clock synchronization and makes the d... » read more

Intel Vs. Everyone Else


A report from ABI Research is starting to gain some attention. For cynics, the question of why now seems perfectly reasonable, considering the report was released early last month and promptly fell well under the semiconductor industry’s radar. But cynicism aside, it’s still interesting to compare specs for chips using ARM’s Cortex-A15, A9 and Qualcomm’s ARM-based Krait. The bottom ... » read more

Medical Drives Boom In MEMS


By Mark LaPedus At a recent event, an executive from a startup called Proteus Digital Health described the medical benefits of swallowing the company’s ingestible sensors or digital pills. First, a consumer would swallow Proteus Digital’s tiny ingestible sensor, along with one’s current medication. With no battery or antenna, the stomach fluid generates the power in the ingestible sen... » read more

VLSI Kyoto – The SOI Papers


By Adele Hars There were some breakthrough FD-SOI and other excellent SOI-based papers that came out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14, 2013). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both were presented in “Jumbo Joint Focus” sessions.  The papers should all b... » read more

The Shape Of Things To Come


By Ed Sperling The standard method of designing chips—by shrinking features and turning up the clock frequency—is running out of steam for many companies. It’s too difficult, too expensive, and without a commercially viable new lithography source it may become even more unrealistic for most applications. That certainly doesn’t mean Moore’s Law is ending, but it could become more o... » read more

Scaling The Lowly SRAM


By Mark LaPedus Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one major challenge that is often overlooked in the equation—scaling the lowly static RAM (SRAM). In one key application, SRAM is the component used to make on-chip cache memories... » read more

The Week In Review: May 31


By Ed Sperling Mentor Graphics and GlobalFoundries teamed up to deliver 20nm design kits that include Mentor’s place and route tool, including verification and conflict resolution engines for double-patterning violations. The 20nm process is used for GlobalFoundries’ 14nm finFETs. Mentor also received 16nm finFET certification from TSMC for the same tools plus its physical verification pl... » read more

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