Viable Choices Ahead

After lots of hand-wringing, several options emerge for cutting power and boosting performance.


Two years ago—basically one process node back, wherever companies were on the Moore’s Law road map—there was confusion about what lies ahead and what is the best way to proceed.

During that time, three very viable options have been proven to work. Some already are in silicon, while others are coming very soon.

The first is the finFET. At the very leading edge of the road map, finFETs have proved to be a workable solution. They dramatically reduce leakage, which can result in lower power, higher performance, or some combination of both. Intel was the first to bat on this one, introducing it at 22nm. Work is now under way by the major foundries to add it at 20, 16 or 14, depending on whose math you actually believe. In some cases, 14nm is actually a combination of 20nm and 14nm technology, while 16nm is something of a bridge between the two.

Still, this is a big step forward. It’s not an easy one, though. The amount of design work needed to double pattern a three-dimensional transistor—and maybe even triple or quadruple pattern it—isn’t something to be taken lightly. It will involve lots of design rules, lots of yield issues, and an enormous amount of extra work.

A second option is fully depleted silicon on insulator, which is being introduced by STMicroelectronics at 28nm. Changing the substrate over to FD-SOI uses the same design flow with a different SPICE model. Compared with finFETs, this is a much easier way to gain performance and power improvements for companies still at the 40nm process node or higher.

The third option is stacked die, and the likely rollout schedule will be 3D memory first, connected through an interposer layer to other components laid out in 2D. While there has been much talk about the added cost of interposers and eventually through-silicon vias, the reality is that it may take far less time and testing to integrate a 2.5D chip in a package than to develop analog IP at 14nm or even 28nm.

Ultimately, most experts believe all three of these approaches will be combined. There finFETs or tunnel FETs at the most advanced nodes on an FD-SOI substrate, and ultimately backing up into stacked die that will defy classification because it will include IP developed at older nodes coupled with the most advanced logic layers. But at least, for now, there are three viable alternatives that have emerged, which means we can all get back to work making it easier to build, implement, test and ultimately manufacture these devices.

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