Week In Review: Design, Low Power

By Jesse Allen - 21 May, 2021 - Comments: 0

Siemens will acquire Supplyframe, a supply chain intelligence, sourcing, and marketplace platform for the electronics industry, for $700 million. The company operates on a software-as-a-service model and will serve as the nucleus of Siemens’ digital marketplace strategy, according to Cedrik Neike, member of the Managing Board of Siemens AG. “Supplyframe’s ecosystem and marketplace intelli... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 21 May, 2021 - Comments: 0

Pervasive computing — IoT, edge, cloud, data center, and back Combining AI with IoT not only gives another acronym AIoT, or Artificial Intelligence of Things, but it puts AI systems on the edge. Infineon Technologies has released its ModusToolbox Machine Learning to make it possible to run deep learning-based workloads on Infineon’s PSoC microcontrollers. The toolbox has middleware, softwa... » read more

How Heterogeneous ICs Are Reshaping Design Teams

By Ed Sperling - 31 Mar, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the complex interactions developing between different engineering groups as designs become more heterogeneous, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Mai... » read more

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing

By eBeam Initiative - 17 Mar, 2021 - Comments: 0

The Survey: 2021 Deep Learning Applications List by eBeam Initiative members is a list of current deep learning efforts that are being used in photomask to wafer semiconductor manufacturing. Examples come from ASML, D2S, Fraunhofer IPMS, Hitachi High-Tech Corporation, imec, Siemens Industries Software, Inc., Siemens EDA, STMicroelectronics, and TASMIT. Published by the eBeam Initiative Membe... » read more

Design Issues For Chips Over Longer Lifetimes

By Ed Sperling - 08 Mar, 2021 - Comments: 0

Semiconductor Engineering sat down to discuss the myriad challenges associated with chips used in complex systems over longer periods of time them with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Maillet-Contoz, system and architec... » read more

Hyperscaling Cyber-Physical Systems

By Frank Schirrmeister - 25 Feb, 2021 - Comments: 0

As consumers, we are not always aware of all the data created around us by our cars, mobile devices, computers, and day-to-day consumer products. In most cases, we are even less aware of what's going on during the development and production of today's devices and systems that we have gotten so used to. During the most recent DATE 2021 conference, the special day on cyber-physical systems gave s... » read more

Big Challenges In Verifying Cyber-Physical Systems

By Ed Sperling - 25 Feb, 2021 - Comments: 0

Semiconductor Engineering sat down to discuss cyber-physical systems and how to verify them with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Maillet-Contoz, system and architect specialist at STMicroelectronics. This discussion was... » read more

Brazil Paves New Semiconductor Path

By Mark LaPedus - 22 Feb, 2021 - Comments: 3

After struggling to get its semiconductor industry off the ground for the last several years, Brazil finally may have found its place in the market with the development of IC design services, memory modules and packaging. Brazil exists well under the radar when it comes to semiconductors. But with little or no fanfare, the nation over the years has been trying to build fabs, assemble chips a... » read more

Marangoni Effect-Based Under-Layer For A Dual Damascene Via-First Approach

By Brewer Science - 17 Feb, 2021 - Comments: 0

One of the main challenges of a Dual Damascene (DD) via-first process is the control of the Critical Dimensions (CDs) in the lithography of the trenches. The PhotoResist (PhR) thickness presents variations from the via arrays to the open areas, which cause the variation of CDs: the swing effect. The planarization of a DD via-first process is reported. A dual-layer solution is used to demonstrat... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 04 Dec, 2020 - Comments: 0

Security The United States Department of Defense added China's SMIC to its blacklist for its alleged cooperation with the Chinese military, reports Reuters. U.S. investors are asked not to invest in SMIC, among 35 other companies based in China on the list. Intel Labs launched the Private AI Collaborative Research Institute with Avast and Borsetta, to advance and develop technologies in pri... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: STMicroelectronics

Week In Review: Design, Low Power

Week In Review: Auto, Security, Pervasive Computing

How Heterogeneous ICs Are Reshaping Design Teams

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing

Design Issues For Chips Over Longer Lifetimes

Hyperscaling Cyber-Physical Systems

Big Challenges In Verifying Cyber-Physical Systems

Brazil Paves New Semiconductor Path

Marangoni Effect-Based Under-Layer For A Dual Damascene Via-First Approach

Week In Review: Auto, Security, Pervasive Computing