tag: Synopsys

Week In Review: Design, Low Power
By Jesse Allen - 06 Sep, 2019 - Comments: 0

Rambus will acquire the Silicon IP, Secure Protocols and Provisioning business from Verimatrix, formerly Inside Secure. The secure silicon IP and provisioning solutions from both companies will be integrated into a single portfolio of products and the embedded security teams from Verimatrix will join Rambus. “Integrating the Verimatrix embedded security team into Rambus, a recognized leader i... » read more

Advantages Of LPDDR5: A New Clocking Scheme
By Brett Murdock - 05 Sep, 2019 - Comments: 5

Earlier this year, JEDEC released the new standard, JESD209–5, Low Power Double Data Rate 5 (LPDDR5). Those that contributed to the development of the standard come from a diverse technology background and represent both manufacturers and consumers of SDRAM memories. Now we have a new memory standard to help enable the future that requires more compute power, higher reliability, and lower pow... » read more

Challenges To Building Level 5 Automotive Chips
By Ann Mutschler - 05 Sep, 2019 - Comments: 0

It’s an exciting time in the automotive space, and this is especially true when it comes to all of the activity around autonomous driving and the path to achieving full Level 5 autonomy. The technology is complex, the ecosystem seems to get more complex by the day, and simulating autonomous systems safely makes this an extremely fascinating area from an engineering perspective. At the heart o... » read more

IP’s Growing Impact On Yield And Reliability
By Ann Mutschler - 04 Sep, 2019 - Comments: 0

Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP. Utilizing poorly qualified IP and waiting for issues to appear during the design-to-verification phase just before tape-out can pose high risks for design houses and foundries alike in terms of cost and time to... » read more

Blog Review: Sept. 4
By Jesse Allen - 04 Sep, 2019 - Comments: 0

Synopsys' Taylor Armerding checks out Apple's newly expanded bug bounty program, with bounty payouts are increasing to compete with malicious actors, and why even with security-oriented development the practice of bug bounties will remain needed. Mentor's Colin Walls shares a few more embedded software tips, this time on external variables, delay loops in real time systems, and meaningful pa... » read more

Enabling Faster Design, Verification and Debug of FPGAs
By Synopsys - 04 Sep, 2019 - Comments: 0

Field programmable gate arrays (FPGAs) are no longer the co-processor of full-custom chips and application-specific integrated circuits (ASICs). Today’s FPGA offerings include devices as large and complex as any ASIC system-on-chip (SoC) on the market. The dramatic increase in size, complexity and functionality means that many FPGA development teams are adopting ASIC-style design, verificatio... » read more

On The Cusp Of 5G
By Kevin Fogarty - 29 Aug, 2019 - Comments: 0

Carriers and chipmakers are celebrating the rollout of the first standards-compliant commercial 5G services. "We are, officially in the era of 5G," said John Smee, vice president of engineering at Qualcomm at the recent 5G Summit at IEEE's International Microwave Symposium (IMS) in Boston. Movement is happening on the commercial end. Major U.S. carriers Verizon, AT&T and Sprint have set ... » read more

Blog Review: Aug. 28
By Jesse Allen - 28 Aug, 2019 - Comments: 0

Cadence's Paul McLellan takes a look at the numerous challenges in designing and manufacturing Cerebras' massive 400,000 processor, 1.2 trillion transistor chip. Synopsys' Taylor Armerding points to a lack of robust mobile app security and why building in security from the beginning can lead to greater productivity and cost saving. Mentor's Paul Johnston takes a look at what's in store at... » read more

EDA Gears Up For 3D
By Brian Bailey - 26 Aug, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor Business Unit of ANSYS; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Bus... » read more

Week In Review: Design, Low Power
By Jesse Allen - 23 Aug, 2019 - Comments: 0

Xilinx debuted the Virtex UltraScale+ VU19P, which the company says is now the world's largest FPGA at 1.6X the size of its predecessor. The VU19P features 35 billion transistors, 9 million system logic cells, up to 1.5 terabits per-second of DDR4 memory bandwidth and up to 4.5 terabits per-second of transceiver bandwidth, and over 2,000 user I/Os. With a set of debug, visibility tools, and IP,... » read more

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