tag: Synopsys

Blog Review: Aug. 28
By Jesse Allen - 28 Aug, 2024 - Comments: 0

Synopsys' Jon Ames checks out how the Ultra Ethernet Consortium aims to revolutionize networking by optimizing Ethernet for the rapidly evolving AI and HPC workloads by addressing critical issues like tail latency that are encountered by machine learning algorithms in large compute clusters. Cadence's Kos Gitchev introduces the DDR5 Multiplexed Rank DIMM (MRDIMM), a memory module technology ... » read more

As EDA Processes Becomes More Secure, So Do Chips
By Adam Kovac - 26 Aug, 2024 - Comments: 0

Security is becoming a much bigger concern within chips and electronic systems, but the actual implementation remains something of an afterthought, which limits its effectiveness. There are many pieces to the security puzzle on the chip design side that go well beyond just securing the hardware or the IP. The EDA tools themselves need to be secure, as well, and so does the user data within t... » read more

Hardware Security Set To Grow Quickly
By Adam Kovac - 22 Aug, 2024 - Comments: 0

Experts At The Table: The hardware security ecosystem is young and relatively small but could see a major boom in the coming years. As companies begin to acknowledge how vulnerable their hardware is, industry standards are being set, but must leave room for engineers to experiment. As part of an effort to determine the best way forward, Semiconductor Engineering sat down with a panel of experts... » read more

Blog Review: Aug. 21
By Jesse Allen - 21 Aug, 2024 - Comments: 0

Cadence's Reela Samuel explores the critical role of PCIe 6.0 equalization in maintaining signal integrity and solutions to mitigate verification challenges, such as creating checkers to verify all symbols of TS0, ensuring the correct functioning of scrambling, and monitoring phase and LTSSM state transitions. Siemens' John McMillan introduces an advanced packaging flow for Intel's Embedded ... » read more

3.5D: The Great Compromise
By Ed Sperling - 21 Aug, 2024 - Comments: 1

The semiconductor industry is converging on 3.5D as the next best option in advanced packaging, a hybrid approach that includes stacking logic chiplets and bonding them separately to a substrate shared by other components. This assembly model satisfies the need for big increases in performance while sidestepping some of the thorniest issues in heterogeneous integration. It establishes a midd... » read more

Chip Industry Week In Review
By The SE Staff - 16 Aug, 2024 - Comments: 0

The U.S. Department of Commerce and Texas Instruments (TI) signed a non-binding preliminary memorandum of terms to provide up to $1.6 billion in CHIPS Act funding towards TI’s investment of over $18 billion for three 300mm semiconductor wafer fabs under construction in Texas and Utah. TI also expects to get about $6 billion to $8 billion from the U.S. Department of Treasury’s Investmen... » read more

Bringing Curvilinear Data To Mask Data Prep
By Al Blais - 15 Aug, 2024 - Comments: 0

Advanced nodes that have been leveraging curvilinear correction with technologies such as ILT and curvilinear OPC are increasingly requiring the use of curvilinear masks to meet advanced feature size and pitch requirements. However, building curvilinear masks with standard OASIS file formats can come at the cost of large file sizes, increased turnaround time, and reduced quality of results. The... » read more

Blog Review: Aug. 14
By Jesse Allen - 14 Aug, 2024 - Comments: 0

Cadence's Dimitry Pavlovsky highlights two new features in the AMBA CHI protocol Issue G update that enhance security of the Arm architecture: Memory Encryption Contexts, which allows data in each Realm in the memory to be encrypted with a different encryption key, and Device Assignment, which introduces hardware provisions to support fully coherent caches in partially trusted remote coherent d... » read more

CPU Performance Bottlenecks Limit Parallel Processing Speedups
By Bryon Moyer - 12 Aug, 2024 - Comments: 0

Multi-core processors theoretically can run many threads of code in parallel, but some categories of operation currently bog down attempts to raise overall performance by parallelizing computing. Is it time to have accelerators for running highly parallel code? Standard processors have many CPUs, so it follows that cache coherency and synchronization can involve thousands of cycles of low-le... » read more

Chip Industry Week In Review
By The SE Staff - 09 Aug, 2024 - Comments: 0

Three Fraunhofer Institutes (IIS/EAS, IZM, and ENAS) launched the Chiplet Center of Excellence, a research initiative to support the commercial introduction of chiplet technology. The center initially will focus on automotive electronics, developing workflows and methods for electronics design, demonstrator construction, and the evaluation of reliability. The UCIe Consortium published the Un... » read more

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