PCIe IP With Enhanced Security For The Automotive Market


The automotive industry is undergoing a rapid transformation, with connectivity and automation becoming integral components of modern vehicles. However, this increased connectivity also brings heightened risks. The automotive industry takes many measures to ensure safety for vehicles, but it is crucial to understand that these safety measures are ineffective if the vehicle's security is comprom... » read more

AI Drives IC Design Shifts At The Edge


The increasing adoption of AI in edge devices, coupled with a growing demand for new features, is forcing chipmakers to rethink when and where data gets processed, what kind of processors to use, and how to build enough flexibility into systems to span multiple markets. Unlike in the cloud, where the solution generally involves nearly unlimited resources, computing at the edge has sharp cons... » read more

Democratizing Roots of Trust from Silicon to Software


With a vast amount of devices getting connected to the Internet of Things (IoT) and the growing number of low-cost attacks being developed to hack such IoT devices, it is clear that the need for embedded security solutions is rising dramatically. A security subsystem in the main system-on-chip (SoC) of a device can be deployed to offer secure cryptographic services to the applications running o... » read more

Big Changes Ahead For Analog Design


Experts at the Table: Semiconductor Engineering sat down to discuss the impact of heterogeneous integration on in-house analog tools, and how that is changing the design process, with Mo Faisal, president and CEO of Movellus; Hany Elhak, executive director of product management at Synopsys; Cedric Pujol, product manager at Keysight; and Pradeep Thiagarajan, principal product manager for custom ... » read more

Blog Review: Nov. 6


Cadence's Satish Kumar C explores how the Deferrable Memory Write transaction type in PCIe and CXL can improve latency, efficiency, and performance by delaying certain memory write operations during system bus congestion or until other priority tasks are complete and highlights implementation and verification challenges. Synopsys' Daryl Seitzer and Rahul Thukral point to magnetoresistive RAM... » read more

Why 40G UCIe IP?


AI applications are bringing new challenges to the semiconductor industry. There is an increased demand for greater bandwidth, especially for compute and networking applications to support the high data processing required by deep learning and machine learning algorithms. The requirements for these AI applications are different for die-to-die interfaces. Let’s take 100Tb networking switches a... » read more

Chiplets Make Progress Using Interconnects As Glue


Breaking up SoCs into their component parts and putting those and other pieces together in some type of heterogeneous assembly is beginning to take shape, fueled by advances in interconnects, complex partitioning, and industry learnings about what works and what doesn't. While the vision of plug-and-play remains intact, getting there is a lot more complicated than initially imagined. It can ... » read more

RISC-V Conformance


Experts At The Table: Despite growing excitement and participation in the development of the RISC-V ecosystem, significant holes remain in the development flow. One of the most concerning is conformance, which must exist before software portability becomes possible. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO... » read more

Blog Review: Oct. 30


Synopsys' Frank Schirrmeister argues that hardware-assisted verification techniques like emulation and prototyping are essential to help engineers improve design behavior to manage complexity and ensure systems function seamlessly in real-world applications. Siemens’ Stephen V. Chavez finds that ultra high-density interconnect (UHDI) has changed the design and production of PCBs to enable ... » read more

Early Architecture Performance and Power Analysis of Multi-Die Designs


Despite the clear advantages of multi-die designs, there are numerous new challenges that stand in the way of multi-die design realization. This white paper focuses on those challenges that can be addressed by early architecture exploration of multi-die designs, including: -System pathfinding -Memory utilization and coherency -Power/thermal management Find out how to overcome such chall... » read more

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