Tuning Design And Process For High-NA EUV Stitching

By Kevin Lucas - 24 Oct, 2024 - Comments: 0

By Kevin Lucas and James Ban Upcoming 14A and 10A process nodes will use high-NA EUV anamorphic scanners, which will require two stitched half-fields to achieve the equivalent wafer exposure area of previous-generation scanners, see figure 1. The lithography patterning at a stitching boundary between two mask exposures will be affected by additional process variation than are encountered in ... » read more

New Approaches To Power Decoupling

By Bryon Moyer - 24 Oct, 2024 - Comments: 0

Decoupling capacitors have long been an important aspect of maintaining a clean power source for integrated circuits, but with noise caused by rising clock frequencies, multiple power domains, and various types of advanced packaging, new approaches are needed. Power is a much more important factor than it used to be, especially in the era of AI. “Doing an AI search consumes 10X the power t... » read more

Reduce Augmented Reality Device Time-to-Market by Bringing Manufacturing Impact to Optical Simulation

By Synopsys - 24 Oct, 2024 - Comments: 0

Disruptive AR systems will push the limits of optics: limits in design, limits in manufacturing, and limits in overall system integration. The trend of optical components being integrated into more complex miniaturized systems is impacting optical software. Optical design software has been around for decades to design, simulate, and analyze any optical component from lenses and mirrors to light... » read more

Americas Chip Funding Energizes Industry

By Liz Allan - 23 Oct, 2024 - Comments: 0

This is the second in a series of articles tracking government chip investments. See part one here (global), part 3 covering EMEA is here and Asia here. Since the first announcement of a non-binding preliminary memorandum of terms with BAE Systems in December 2023, the U.S. Department of Commerce has rolled out comprehensive plans to support more than a dozen companies in order to shore up... » read more

Blog Review: Oct. 23

By Jesse Allen - 23 Oct, 2024 - Comments: 0

Cadence’s Sanjeet Kumar introduces the message bus interface in the PHY Interface for the PCIe, SATA, USB, DisplayPort, and USB4 Architectures (PIPE) specification, which provides a way to initiate and participate in non-latency-sensitive PIPE operations using a small number of wires. Siemens’ Dennis Brophy argues that the recently published Portable Test and Stimulus Standard (PSS) 3.0 ... » read more

Increasing Design Flexibility With RISC-V-Based Processor IP

By Rich Collins - 21 Oct, 2024 - Comments: 0

The semiconductor industry increasingly needs more flexible and scalable processor architectures, driving the growing adoption of RISC-V. Originally developed at the University of California, Berkeley, the open-source RISC-V instruction set architecture (ISA) has become very popular in recent years. RISC-V allows designers to customize their processor implementations to meet the specific needs ... » read more

LLMs Show Promise In Secure IC Design

By Adam Kovac - 21 Oct, 2024 - Comments: 0

The introduction of large language models into the EDA flow could significantly reduce the time, effort, and cost of designing secure chips and systems, but they also could open the door to more sophisticated attacks. It's still early days for the use of LLMs in chip and system design. The technology is just beginning to be implemented, and there are numerous technical challenges that must b... » read more

3DIO IP For Multi-Die Integration

By Lakshmi Jain - 17 Oct, 2024 - Comments: 0

By Lakshmi Jain and Wei-Yu Ma The demand for high performance computing, next-gen servers, and AI accelerators is growing rapidly, increasing the need for faster data processing with expanding workloads. This rising complexity presents two significant challenges: manufacturability and cost. From a manufacturing standpoint, these processing engines are nearing the maximum size that lithogra... » read more

How Big A Deal Is Aging?

By Brian Bailey - 17 Oct, 2024 - Comments: 0

Nothing lasts forever, but in the semiconductor world things used to last long enough to become obsolete long before their end of life. That's no longer the case with newer nodes, and it is raising concerns in safety-critical markets such as automotive. Being able to fully understand what happens inside of chips is still a work in progress, and analysis approaches are trying to keep up. Unti... » read more

Unbundling Analog From Digital Where It Makes Sense

By Ed Sperling - 17 Oct, 2024 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing in analog design with the shift toward heterogeneous integration and more safety- and mission-critical applications with Mo Faisal, president and CEO of Movellus; Hany Elhak, executive director of product management at Synopsys; Cedric Pujol, product manager at Keysight; and Pradeep Thiagarajan, principal product manager for custom I... » read more

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tag: Synopsys

Tuning Design And Process For High-NA EUV Stitching

New Approaches To Power Decoupling

Reduce Augmented Reality Device Time-to-Market by Bringing Manufacturing Impact to Optical Simulation

Americas Chip Funding Energizes Industry

Blog Review: Oct. 23

Increasing Design Flexibility With RISC-V-Based Processor IP

LLMs Show Promise In Secure IC Design

3DIO IP For Multi-Die Integration

How Big A Deal Is Aging?

Unbundling Analog From Digital Where It Makes Sense

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