Why Your FPGA Synthesis Flow Requires Verification

By Tom Anderson - 26 Apr, 2018 - Comments: 0

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL language that looks more like software than hardware, and implements it using the low-level building-block library of an ASIC or FPGA device. The resulting gate-level netlist must meet a variety of requir... » read more

IP And Power

By Brian Bailey - 08 Mar, 2018 - Comments: 0

[getkc id="108" kc_name="Power"] is quickly becoming a major differentiator for products, regardless of whether they are connected to a wall outlet or dependent on a battery. At the same time, increasing amounts of a chips content comes from third-party [getkc id="43" kc_name="IP"]. So how do system designers ensure that the complete system has an optimal power profile, and what can they do to ... » read more

Reflection On 2017: Design And EDA

By Brian Bailey - 03 Jan, 2018 - Comments: 0

People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. We see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but most have this year. (Part one looked at the predictions associated with s... » read more

Finite State Machine Synthesis In Programmable Circuits

By Radek Nawrot - 28 Sep, 2017 - Comments: 0

Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine of working on so many revisions? For me, one of my summer break ponderings was thinking back on a trick I learned while working with my colleagues at the Silesian University of Technology. C... » read more

IP Challenges Ahead

By Brian Bailey - 10 Aug, 2017 - Comments: 0

The revenue from semiconductor [getkc id="43" kc_name="IP"] has risen steadily to become the largest segment of the EDA industry. Industry forecasts expect it to keep growing at a CAGR of more than 10% for the next decade. Part one of this article examined the possibility those forecasts are wrong and that large semiconductor companies are likely to start bringing IP development back in hous... » read more

The Problem With Clocks

By Brian Bailey - 13 Apr, 2017 - Comments: 1

The synchronous digital design paradigm has enabled us to design circuits that are well controlled, but that is only true if the clocks themselves are well controlled. While overdesign techniques ensured that to be the case in early ASIC development, designs today cannot afford such luxuries. As we strive for lower power and higher operating frequencies, the clock has become a critical desig... » read more

The Path To (Virtually) Zero Defective Parts Per Million

By Synopsys - 22 Feb, 2017 - Comments: 0

Despite thorough wafer and package testing, a small number of defective ICs can make their way into systems. These test "escapes" often return as field failures, increasing costs and eroding profit margins. They can also present a hazard if deployed in safety-critical systems, which is why companies purchasing semiconductors for automotive, medical, or aerospace applications often demand a zero... » read more

What’s The Real Benefit Of High-Level Synthesis?

By Dave Pursley - 10 Nov, 2016 - Comments: 0

Once upon a time, “behavioral synthesis,” the precursor to high-level synthesis, hung its hat on design productivity as its sole value. By that, I mean, if a behavioral synthesis tool provides a high enough productivity benefit, designers or design managers will boil the ocean to move to it. There was little methodology around it. In fact, even the design entry language was unfamiliar. Yes,... » read more

The Time Dimension Of Power

By Brian Bailey - 10 Nov, 2016 - Comments: 0

Power is the flow of energy over time. While both aspects of that equation are important, they are important to different people in different ways. Energy that moves too quickly can cause significant damage. Too much energy moving over time can mean a non-competitive product, from battery-powered devices to a wide array of locations such as the datacenter. When the industry talks about power... » read more

Three Power-Saving Techniques Using PCI Express IP

By Synopsys - 09 Nov, 2016 - Comments: 0

The increasing data traffic between devices in a computing application environment is causing a large power footprint, and for that reason designers are looking for ways to lower the power consumption of their SoCs during sparse or idle times. The smaller, battery-powered devices are often idle and in deep sleep modes, but these deep power saving modes come at the cost of slow resume times to s... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?