SoC + AI = SiPx

By Rich Wawrzyniak - 15 Feb, 2018 - Comments: 0

The market for third-party semiconductor intellectual property (SIP) continues to exhibit growth well beyond the (CAGR) Compound Annual Growth Rate for the semiconductor industry. Semico just completed an in-depth analysis and breakdown of the SIP market in a report called Licensing, Royalty and Service Revenues For 3rd Party SIP (SC105-18). The 2017 to 2022 CAGR is projected to be 10.9%, about... » read more

Fan-Out Wars Begin

By Mark LaPedus - 05 Feb, 2018 - Comments: 3

Several packaging houses are developing the next wave of high-density fan-out packages for premium smartphones, but perhaps a bigger battle is brewing in the lower density fan-out arena. Amkor, ASE, STATS ChipPAC and others sell traditional low-density fan-out packages, although some new and competitive technologies are beginning to appear in the market. Low-density fan-out, or sometimes cal... » read more

Fan-Out Wafer Level eWLB Technology As An Advanced System-in-Package Solution

By STATS ChipPAC - 05 Feb, 2018 - Comments: 0

System-in-Package (SiP) technology continues to be essential for higher integration of functional blocks to meet the ever demanding market needs with respect to smaller form factor, lower cost and time to market. A typical SiP incorporates all or some form of Fan-Out Wafer Level packaging, wire bonding or flip chip that serves a multitude of applications such as optoelectronics, RF, power ampli... » read more

Packaging Challenges For 2018

By Mark LaPedus - 08 Jan, 2018 - Comments: 0

The IC packaging market is projected to see steady growth this year, amid ongoing changes in the landscape. The outsourced semiconductor assembly and test ([getkc id="83" kc_name="OSAT"]) industry, which provides third-party packaging and test services, has been consolidating for some time. So while sales rising, the number of companies is falling. In late 2017, for example, [getentity id="2... » read more

Fan-Out Wafer Level eWLB Technology As An Advanced System-In-Package Solution

By STATS ChipPAC - 08 Jan, 2018 - Comments: 0

Mixed-Signal Issues Worse At 10/7nm

By Ann Mutschler - 03 Jan, 2018 - Comments: 1

Despite increasingly difficulty in scaling digital logic to 10/7nm, not all designs at the leading edge are digital. In fact, there are mixed-signal components in designs at almost all nodes down to 10/7nm. This may seem surprising because analog scaling has been an issue since about 90nm, but these are not traditional analog components. Analog IP increasingly includes highly integrated, mix... » read more

What’s What In Advanced Packaging

By Choon Lee - 16 Nov, 2017 - Comments: 5

Ever open the body of your smartphone (perhaps unintentionally) and see small, black rectangles stuck on a circuit board? Those black rectangles are packaged chips. The external chip structure protects the fragile integrated circuits inside, as well as dissipates heat, keeps chips isolated from each other, and, importantly, provides connection to the circuit board and other elements. The manufa... » read more

Effective Management Of System Designs

By Ranjit Adhikary - 08 Nov, 2017 - Comments: 0

With the advent of the Internet-of-Things (IoT), system designs are slowly but surely becoming more complex. They now use heterogeneous architectures both on the System-on-Chip (SoC) and within a package. These systems typically have multiple different CPU cores, hardware accelerators, memories, network-on-chip (NoC) fabrics and numerous peripheral interfaces. Now, add to this the complexiti... » read more

Where MEMS Can Boldly Go Now

By Jeff Dorsch - 06 Nov, 2017 - Comments: 1

MEMS chips are being designed to go into the human body as biosensors, which will require unique packaging. And as demand grows for assisted and automated driving, MEMS devices also are finding new use cases in automotive electronics, their chief market segment prior to the millennium. Pressure sensors, such as those that monitor the air pressure in tires, remain the biggest type of [getkc i... » read more

Noise Abatement

By Brian Bailey - 12 Oct, 2017 - Comments: 0

[getkc id="285" kc_name="Noise"] is a fact of life. Almost everything we do creates noise as a by-product and quite often what is a signal to one party is noise to another. Noise cannot be eliminated. It must be managed. But is noise becoming a larger issue in chips as the technology nodes get smaller and packaging becomes more complex? For some, the answer is a very strong yes, while for ot... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

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Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

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by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

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