Mixed-Signal Issues Worse At 10/7nm

Putting as much functionality into digital circuitry helps, but it’s becoming more difficult for these two worlds to exist on a single die at each new node.


Despite increasingly difficulty in scaling digital logic to 10/7nm, not all designs at the leading edge are digital. In fact, there are mixed-signal components in designs at almost all nodes down to 10/7nm.

This may seem surprising because analog scaling has been an issue since about 90nm, but these are not traditional analog components. Analog IP increasingly includes highly integrated, mixed-signal type of circuits, such as PLLs.

“In some cases the analog and mixed-signal capabilities — or custom and mixed-signal capabilities —are needed because the number of advanced processes effects such that some things have to be done in a more custom way,” said Mladen Nizic, product management director in the Custom IC & PCB Group at Cadence.

Unlike digital circuitry, analog circuits do not directly benefit from scaling. Reducing the size of analog components does not improve performance or lower power, and increased density and proximity to noisy, leaky digital circuits can disrupt the smooth waves in analog designs. That has prompted a number of efforts over the years to replace analog with digital circuits, but after decades of work analog still has a solid foothold in chip design. We live in an analog world that cannot be accurately represented with purely digital design. Still, these two worlds can be fused together in a way that reduces the amount of analog circuitry, pushing as much functionality as possible to the digital side to make scaling easier than if all the functionality was put into analog circuitry.

Fig. 1: Analog signals. Source: Analog Devices

Fig. 2: Digital signals. Source: Illinois Institute of Technology

“The concept of pure analog is long gone,” said Oliver King, CTO at Moortec. “That changes things because when you look at analog characterization at finFET nodes, it’s not just about recharacterization from previous nodes. It’s often a ground-up redesign or re-implementation. Constraints are tight, and you get less use out of a design than you used to at 60nm.”

Among the constraints that need to be considered are power and thermal management. Both are increasingly critical factors in designs at 90nm and below, and they are particularly important when it comes to mixed signal.

“In digital today, the majority of a design’s power is actively managed now,” said Cadence’s Nizic. “We see that becoming quite common in the analog and mixed-signal. Power techniques are now being applied in mixed-signal designs, which means not only device level like back biasing and multi-threshold, but also different power domains, power shut-off and then some amount of logic to control that behavior in order to minimize the power for the task at any given time. This impacts analog and digital content within a mixed-signal design, whether it is within a block or IP or the SoC, creating additional challenges in verification.”

For each different power mode, the design must function correctly and perform at least according to spec. “The verification challenge is already significant, but now it gets multiplied by a number of different power modes,” Nizic noted. “For this purpose today, both dynamic and static methods have to be used and applied in the mixed signal portion of the design. In digital this is quite well defined but now analog is catching up.”

Performance matters
Performance becomes a more complex equation in mixed signal designs, as well.

“Sometimes that’s next-generation speeds like USB 3.1 or USB 3.2, which is double the speed of USB 3.1, so you’re going from 10 gigabits per second to 20 gigabits per second, that’s a big jump,” said Navraj Nandra, senior director of product marketing for Interface IP at Synopsys. “Or it’s moving from PCI Express 4.0, which is 16 gigatransfers per second (GT/S), to PCIe 5.0, which is 32 GT/s, yielding 128 GB/s in full duplex networking configurations. All the while, users ask the IP to be implemented in a next-generation process technology like 16 or 14nm finFET, or even 7nm finFET, which is starting to crop up as an important technology node. With the technology feature size reduction and the higher speeds, design teams are also expecting lower power.”

Much of this is being driven by big data/big data analytics/machine learning/artificial intelligence market is pushing power requirements in addition to datacenters, Nandra said.

“Some data centers are in countries that have diesel generators,” said Nandra. “So the calculation is based on how much ‘on’ time is needed for the compute farm, which might be doing some kind of service-type requirement like analytics in a hospital because everything is data processing, regardless of wherever you are based in the world. Everything is data processing by computer and there is so much data being generated. There are big server farms located around the world, and some locations don’t have the energy or electricity infrastructure, so the semiconductor technology has advanced a lot further than the electrical infrastructure. As a result, these places need very low power servers because they don’t have enough diesel to keep their plants running for the generators. But even if the energy source is plentiful, there are problems with cooling. The air conditioning is more of an issue than the actual size of the chip, in a way. So these companies are asking for lower power.”

Of course, users want all of this at lower cost, Nandra said. “Much of Moore’s Law is driven by cost. It’s all about putting more integration onto a chip to reduce the overall system cost. While many people don’t think about it from the cost viewpoint, actually that’s the whole point. Moore’s Law is all about reducing costs. In an engineering environment, we always talk about power, area, performance. We don’t think about cost as a design variable, but it is.”

At 7nm, for analog/mixed-signal IP, the providers of this IP have continued to follow the scaling technology. “We’ve got silicon back on 7nm, so it’s working for our analog/mixed-signal IP. I don’t see any issue in developing 7nm mixed-signal IP,” Nandra said.

However, in order to actually develop 7nm IP, there is a big investment, which only the leading IP providers can make. This has opened discussions around the industry about partitioning the design—whether that happens on one die or in a package with multiple chips—so the digital functionality can be developed at the leading-edge node and the analog/mixed signal is developed at an older node. The advantage of the latter approach is that the analog/mixed-signal IP doesn’t need to be redeveloped with every process generation because more of the design can be kept in an established process node.

Integration and packaging issues
Add to this the challenges of integrating analog with digital. “This is still hard, especially in advanced nodes primarily because while the digital portion is shrinking, and applications want to take advantage of the shrinking nodes to get better performance and lower power, at the same time the analog portion doesn’t quite fit into those process nodes,” said Nebabie Kebebew, senior product manager, analog/mixed-signal verification at Mentor, a Siemens Business. “It doesn’t work there, specifically in high precision analog designs, because when you try to fit that into the shrinking nodes the performance is impaired/impacted.”

As for how much the performance is impacted, it is hard to pin down a figure because it is a design-specific metric. What it comes down to is that with the shrinking of advanced nodes, noise increases with the amount of switching parts at high frequency, Kebebew pointed out. “This becomes a conduit for noise, and noise is not a good thing for high precision analog and RF circuits especially architectures that are sensitive to noise.”

She’s not alone in seeing these problems. “About 80% of design starts are high frequency or high speed,” said Yorgos Koutsoyannopoulos, president and CEO of Helic. “With a typical package, there is no way to absorb radiation, so we’re seeing channels that propagate noise, or noise in the power grid itself. You’re dealing with a maximum amount of metal, so you care a lot about the analysis because you need to know the magnitude of the problem. We’re still in that stage as a community. We’re talking about how to quantify this issue and figuring out what is the aggressor, what is the victim, and what is the risk.”

Back-end metallization, inter-symbol interference (ISI), channel plus package loss, and crosstalk are major concerns in today’s advanced A/MS designs, especially in high-performance and high-speed serial links at 28, 56, and 112Gbps data rates, explained Nhat Nguyen, senior director, engineering, MID marketing at Rambus. “Today’s advanced finFET processes present significant challenges in AMS designs due to poor back-end via and metallization. These challenges are further exacerbated with strict current density and EM rules. Equalization techniques such as CTLE, FIR/FFE, and DFE can be used to circumvent ISI.  Advanced packaging, in conjunction with well-designed I/O bumpout and package ballout, can help minimize signal loss and crosstalk noise, hence improving the signal-to-noise (SNR) ratio. It is very desirable to limit the package loss to about 10% of the total loss.”

Indeed, moving non-shrinking components, such as inductors or transmission lines, to an advanced package will help to reduce the analog part also in advanced nodes, noted Andy Heinig, group manager system integration at Fraunhofer EAS. “For example, such an approach is demonstrated with inductors for PLLs in SerDes IP. The moving also helps to increase the performance of the inductor (and as a result the performance of the analog block) because of better materials available in the package compared to silicon.”

The many dynamics of analog/mixed-signal design at advanced nodes lends itself to more opportunistic packaging, Mentor’s Kebebew suggested. “The trend is moving towards this especially now that the need to have a single IC is no longer there. You can have multiple dies on one package, and therefore, you need to separate the digital on the advanced nodes and then the analog on the more mature nodes and have separate packaging. That way you are isolating the analog and the digital, and minimizing the amount of noise source to the analog portion.”

As for the specific point in time that this became necessary varies depending on the application, but the general consensus is this became an issue at about 90nm for these types of high precision analog and RF circuits.

Analog designs for automotive applications that deal with very high voltages also require increasingly sophisticated packaging approaches because the high voltages are not suitable for digital or advanced nodes. The transistor junction would burn up if subjected to these high voltages. “This has led to system-in-package approaches and multi chip modules, where there the analog and digital portions are isolated, and in some cases, some of the passive components are actually right on the silicon, as well, Kebebew said. “The goal is to minimize the noise interference so that it is a high-performing chip.”

New tradeoffs
While some of the same power techniques used in digital design can be used at the mixed-signal level, every analog designer would try to design circuits choosing the right topology to minimize the power and still meet the performance, Cadence’s Nizic said.

“When we raise the level up, what designers also like is to have the ability to make tradeoffs between performance and power when it comes to analog, as well. For example, as we have seen in digital design, if I operate at 800MHz I know how much power I’ve consumed. If I can lower the clock frequency somewhere, I know I can save some power and I can basically understand the dependency and then choose what’s optimal for the SoC or system that I’m designing. This is emerging as a need for analog, as well, because in some cases we might be able to trade a little bit of some of the performance in order to save power at the system level or at the SoC level. For that, methodology and tools are emerging with support in this area,” Nizic said

It’s important to keep in mind with analog/mixed-signal design at advanced nodes that what used to be second-order effects are now first-order physical device effects, and these are only becoming more prominent, Kebebew noted. To account for this, she advised that when taping out a design, robust characterization is critical.

“That’s where the environment driving that solution becomes key in order to set up the verification to run robust characterization to cover all of the corners,” she said. “From a designer standpoint, this means brute force — running everything, including all of the corners that the foundry supplies, along with statistical Monte Carlo simulation. If they had all the time in the world, the verification team would run the entire set, but usually they don’t have enough time so they have to look at the limited set. Where is the cut-off point? Being able to drive that and knowing where that is requires an environment that allows for the monitoring of the coverage across the design blocks in the analog/mixed-signal realm. Being able to have visibility as to what’s going on across the different parameters or variations that they are simulating against is key. Access and visibility is critical for each block in a design.”

—Ed Sperling contributed to this report.

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Kev says:

They have not fixed the issues of mixing analog and digital in general, let alone at 10nm. It’s hard because the digital guys run the design methodology and they are clueless about analog, and have failed to do things like merge Verilog-AMS and SystemVerilog (and neither of them work properly anyway). That’s fixable (just ask me).

The actual problem of designing analog at 10nm is less of an issue than people think because there are a lot of old circuits for dealing with mismatched transistors from board-level design days, but for the last few decades the analog guys have been used to just drawing nicely matched things on Silicon, and have forgotten the old ways – time for a trip to the library.

You are also better of on FDSOI than FinFETS if you need to do analog.

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