Optimizing Data Movement


Demand for new and better AI models is creating an insatiable demand for more processing power and much better data throughput, but it's also creating a slew of new challenges for which there are not always good solutions. The key here is figuring out where bottlenecks might crop up in complex chips and advanced packages. This involves a clear understanding of how much bandwidth is required ... » read more

Future-proofing AI Models


Experts At The Table: Making sure AI accelerators can be updated for future requirements is becoming essential due to the rapid introduction of new models. Semiconductor Engineering sat down to discuss the challenges of future-proofing these designs with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vic... » read more

AI Accelerators Moving Out From Data Centers


Experts At The Table: The explosion in AI data is driving chipmakers to look beyond a single planar SoC. Semiconductor Engineering sat down to discuss the need for more computing and the expanding role of chiplets with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vice president of marketing at Expedera; ... » read more

Designing For Multiple Die


Integrating multiple die or chiplets into a package is proving to be very different than putting them on the same die, where everything is developed at the same node using the same foundry process. As designs become more heterogeneous and disaggregated, they need to be modeled, properly floor-planned, verified, and debugged in the context of a system, rather than as individual components. Typi... » read more

IP Industry Transformation


The design IP industry is developing an assortment of new options and licensing schemes that could affect everything from how semiconductor companies collaborate to how ICs are designed, packaged, and brought to market. The IP market already has witnessed a sweeping shift from a "design once, use everywhere" approach, to an "architect once, customize everywhere" model, in which IP is highly ... » read more

Automotive Bandwidth Issues Grow As Data Skyrockets


Bandwidth requirements for future vehicles are set to explode as the amount of data moving within vehicles, between vehicles, and between vehicles and infrastructure, continues to grow rapidly. That data will be necessary for a variety of functions, some of which are here today and many of which are still in development. On the safety side, that includes everything from early warning systems... » read more

Advances In EM Analysis And Design Flows For RF System Development


With the move toward higher frequencies and component densities, RF/mixed signal PCB systems and heterogeneous system-in-package (SiP) technologies are increasingly susceptible to delayed product development turnaround times that threaten delivery schedules. These delays often occur late in development during integration when components that met the design specifications fail to achieve the req... » read more

Architecting Interposers


An interposer performs a similar function as a printed circuit board (PCB), but when the interposer is moved inside a package the impact is significant. Neither legacy PCB nor IC design tools can fully perform the necessary design and analysis tasks. But perhaps even more important, adding an interposer to a design may require organizational changes. Today, leading-edge companies have shown ... » read more

Using ML In EDA


Machine learning is becoming essential for designing chips due to the growing volume of data stemming from increasing density and complexity. Nick Ni, director of product marketing for AI at Xilinx, examines why machine learning is gaining traction at advanced nodes, where it’s being used today and how it will be used in the future, how quality of results compare with and without ML, and what... » read more

Recalculating The Cost Of Test


The cost of test is rising. For decades, test was limited to a flat 2% of the cost of designing and manufacturing a chip. Today, no one is quite sure what that cost really is, and there doesn't seem to be any single formula for determining it. In some cases, there isn't even a sense of urgency to finding out. Several significant changes are occurring that make any formula difficult to cal... » read more

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